Implementing a chaotic cryptosystem in a 64-bit embedded system by using multiple-precision arithmetic

Abstract

This paper proposes a new chaotic cryptosystem for the encryption of very high-resolution digital images based on the design of a digital chaos generator by using arbitrary precision arithmetic. This can be taken as an alternative to reduce the dynamic degradation that chaotic models present when they are implemented in digital devices and to increase the security of the cryptosystems. The obtained results show that when using high-precision arithmetic, the generated sequences provide good randomness and security during a greater number of iterations of the implemented chaotic maps in comparison with the generated sequences by using the standard of simple precision or double precision according to the IEEE 754 standard for floating-point arithmetic. The proposed method does not require high-cost hardware for increasing the numerical accuracy and security. As an advantage versus other recent works, using high precision, in relation to the methods that use simple precision or double precision, it awards an exponential increase in the key space. In this manner, it is demonstrated that using multiple-precision arithmetic, a key space of \(2^{33,268}\) or higher can be obtained, depending on the level of high precision configured. The security analysis confirms that the proposed chaotic cryptosystem is secure and robust against several known attacks, as well as statistical tests of NIST and TestU01, proving that high-precision arithmetic helps to enhance the security of the cryptosystems.

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Acknowledgements

This paper was supported by the research project approved at the 18th Internal Call for Research Projects by UABC, with number 485. The researchers A.F.V. and E.R.O. were supported for his postgraduate studies at PhD level by CONACyT. Thanks to PRODEP (Professional Development Program for Professors) for supporting the new generations and for innovating the application of knowledge with the Number 402/377/E. The authors would like to express their gratitude to TECNM for financial support under project 6578.18-P.

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Flores-Vergara, A., García-Guerrero, E.E., Inzunza-González, E. et al. Implementing a chaotic cryptosystem in a 64-bit embedded system by using multiple-precision arithmetic. Nonlinear Dyn 96, 497–516 (2019). https://doi.org/10.1007/s11071-019-04802-3

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Keywords

  • Chaotic cryptography
  • Digital degradation
  • floating-point arithmetic
  • Arbitrary precision arithmetic
  • Embedded system