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FPGA realization of a chaotic communication system applied to image processing

Abstract

The hardware realization of a chaotic communication system from the description of continuous-time multi-scroll chaotic oscillators is introduced herein by using field-programmable gate arrays (FPGA). That way, two multi-scroll chaotic oscillators generating 2 and 6 scrolls are synchronized by applying Hamiltonian forms and observer approach. The synchronized master-slave topology is used to implement a secure communication system by adding chaos to an image at the transmission stage and by subtracting chaos at the recover stage. The FPGA realization begins by applying numerical methods to solve the system of equations describing the whole chaotic communication system. Further, the replacement of multipliers by single constant multiplication blocks reduces the use of hardware resources and accelerates the processing time as well. Using chaotic oscillators with 2 and 6 scrolls, three kinds of images are processed: one in black and white and two in gray tones. Finally, the experimental results confirm the appropriateness on realizing chaotic communication systems for image processing by using FPGAs.

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Acknowledgments

This work is partially supported by CONACyT/Mexico under projects 237991 and 136056.

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Correspondence to E. Tlelo-Cuautle.

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Tlelo-Cuautle, E., Carbajal-Gomez, V.H., Obeso-Rodelo, P.J. et al. FPGA realization of a chaotic communication system applied to image processing. Nonlinear Dyn 82, 1879–1892 (2015). https://doi.org/10.1007/s11071-015-2284-x

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  • DOI: https://doi.org/10.1007/s11071-015-2284-x

Keywords

  • FPGA
  • Synchronization
  • Hamiltonian forms
  • Multi-scroll chaotic oscillator
  • Single constant multiplication block
  • Numerical methods
  • Computer arithmetic