The Finite Impulse Response (FIR) filter plays an important role in many signal processing applications. This manuscript proposes an intuitive adaptive filter based on fixed-point finite impulse response with approximate distributed arithmetic (DA) circuits. For digital signal and image processing requirements, several floating-point multiplications are mandatory. The floating point multiplication is implied by the canonically signed integer (CSD) and contrasts with the conventional multiplication technique. Moreover, a new multiplier method is introduced that translates 2's supplement into CSD in real time. The Booth algorithm is a multiplication algorithm that uses two additional notations of signed bits to multiplier multiplication. The Booth approach allows the count of partial products (PPs) to be diminished efficiently through categorizing consecutive bits to the multitude of signed multiples as one of the operands. The operand encoded by Booth is known as the multiplier and the other operand is called multiplicand. By incorporating the CSD and approximate booth recode (ABR) number representation in the multiplier and improving multiplier output and energy consumption the number of non-zero components is minimized. An intensive DA-based approach is proposed on the technology based on an exact and optimized dispersed arithmetic, which reconfigures finite impulse response filters, whose filter coefficients transition in runtime. The algorithm of this prototype is used to restrict the number of component DA products with the CSD and ABR, although there is no explicit multiplication. The partial products are provided by decreasing data input by offsetting errors. A wallace tree is known for its partial product accumulation that reduces the cost of hardware. The proposed hardware design reduces partial non-zero products to minimum and restricts the number of arithmetic operations in the carrying saved device. The proposed architectural framework is implemented in Verilog with a Xilinx 14.5 ISE simulation. Utilization of hardware is reduced and also critical path delay of the propose architecture is reduced to 5 s. Maximum operating frequency of the proposed architecture is 126.9 MHz. The experimental results demonstrate that the proposed motion estimation algorithm has better performance likened to the existing works.
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Ahn, C. K., Shmaliy, Y. S., & Shi, P. (2016). Generalized dissipativity-based receding horizon FIR filtering with deadbeat property. IEEE Transactions on Circuits and Systems II: Express Briefs.
Ali, N., & Garg, B. (2017). New energy efficient reconfigurable fir filter architecture and its vlsi implementation. In: International Symposium on VLSI Design and Test (pp. 519–532). Springer, Singapore.
Amanollahi, S., & Jaberipur, G. (2017). Fast energy efficient radix-16 sequential multiplier. IEEE Embedded Systems Letters, 9(3), 73–76
Burgess, R. C. (2019). Filtering of neurophysiologic signals. Handbook of Clinical Neurology, 160, 51–65
Capizzi, G., Coco, S., Sciuto, G. L., & Napoli, C. (2018). A new iterative FIR filter design approach using a Gaussian approximation. IEEE Signal Processing Letters, 25(11), 1615–1619
Chandra, A., & Chattopadhyay, S. (2016). Design of hardware efficient FIR filter: a review of the state-of-the-art approaches. Engineering Science and Technology, an International Journal, 19(1), 212–226
Chen, L., Liu, M., Wu, J., Yang, J., & Dai, Z. (2019). Structure evolution-based design for low-pass IIR digital filters with the sharp transition band and the linear phase passband. Soft Computing, 23(6), 1965–1984
Darvish-Molla, S., Chin, K., Prestwich, W. V., & Byun, S. H. (2018). Development of a compact and cost effective multi-input digital signal processing system. Nuclear Instruments and Methods in Physics Research Section A: Accelerators, Spectrometers, Detectors and Associated Equipment, 879, 13–18
Guyette, A. C., Naglich, E. J., & Shin, S. (2017). RF-power-activated and signal-tracking tunable bandstop filters. IEEE Transactions on Microwave Theory and Techniques, 65(5), 1534–1544
Haridas, N., & Elias, E. (2016). Design of reconfigurable low-complexity digital hearing aid using Farrow structure based variable bandwidth filters. Journal of Applied Research and Technology, 14(2), 154–165
Işıker, H., & Özdemir, C. (2020). Adaptation of stepped frequency continuous waveform to range-Doppler algorithm for SAR signal processing. Digital Signal Processing, 106, 102826
Jiang, H., Han, J., Qiao, F., & Lombardi, F. (2015). Approximate radix-8 booth multipliers for low-power and high-performance operation. IEEE Transactions on Computers, 65(8), 2638–2644
Jiang, H., Liu, C., Liu, L., Lombardi, F., & Han, J. (2017). A review, classification, and comparative evaluation of approximate arithmetic circuits. ACM Journal on Emerging Technologies in Computing Systems (JETC), 13(4), 1–34
Jiang, H., Liu, L., Jonker, P. P., Elliott, D. G., Lombardi, F., & Han, J. (2018). A high-performance and energy-efficient FIR adaptive filter using approximate distributed arithmetic circuits. IEEE Transactions on Circuits and Systems I: Regular Papers, 66(1), 313–326
Jyothi, G. N., Sanapala, K., & Vijayalakshmi, A. (2020). ASIC implementation of distributed arithmetic based FIR filter using RNS for high speed DSP systems. International Journal of Speech Technology, 23, 1–6
Khan, M. T., & Ahamed, S. R. (2017). A new high performance VLSI architecture for LMS adaptive filter using distributed arithmetic. In Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI (ISVLSI) (pp. 219–224). IEEE.
Morgan, K. D., & Noehren, B. (2018). Identification of knee gait waveform pattern alterations in individuals with patellofemoral pain using fast Fourier transform. PLoS ONE, 13(12), e0209015
Mythili, S., Thiyagarajah, K., Rajesh, P., & Shajin, F. H. (2020). Ideal position and size selection of unified power flow controllers (UPFCs) to upgrade the dynamic stability of systems: an antlion optimiser and invasive weed optimisation algorithm. HKIE Transaction, 27(1), 25–37. https://doi.org/10.33430/V27N1THIE-2018-0024
Odugu, V. K., Narasimhulu, C. V., & Prasad, K. S. (2020). Design and implementation of low complexity circularly symmetric 2D FIR filter architectures. Multidimensional Systems and Signal Processing, 31, 1–26
Transpire Online. (2019). The Feedback Artificial Tree Algorithm (FAT): Great Potential to Solve Wide Range of Practical Optimization Problems, Transpire Online 2019. https://transpireonline.blog/2020/05/29/the-feedback-artificial-tree-algorithm-fat-great-potential-to-solve-wide-range-of-practical-optimization-problems/. Accessed Sep 2019
Pak, J. M., Ahn, C. K., Shmaliy, Y. S., Shi, P., & Lim, M. T. (2015). Switching extensible FIR filter bank for adaptive horizon state estimation with application. IEEE Transactions on Control Systems Technology, 24(3), 1052–1058
Prabakaran, H. B. K., & Yada, A. (2019). High throughput parallelized realization of adaptive fir filter based on distributive arithmetic using offset binary coding. In Proceedings of the 2019 10th International Conference on Computing, Communication and Networking Technologies (ICCCNT) (pp. 1–6). IEEE.
Qiqieh, I., Shafik, R., Tarawneh, G., Sokolov, D., Das, S., & Yakovlev, A. (2018). Significance-driven logic compression for energy-efficient multiplier design. IEEE Journal on Emerging and Selected Topics in Circuits and Systems, 8(3), 417–430
Rajesh, P., & Shajin, F. (2020). A multi-objective hybrid algorithm for planning electrical distribution system. European Journal of Electrical Engineering., 22(4–5), 224–509. https://doi.org/10.18280/ejee.224-509
Ray, D., George, N. V., & Meher, P. K. (2018). Efficient shift-add implementation of FIR filters using variable partition hybrid form structures. IEEE Transactions on Circuits and Systems I: Regular Papers, 65(12), 4247–4257
Rojo-Álvarez, J. L., Martínez-Ramón, M., Marí, J. M., & Camps-Valls, G. (2018). Digital signal processing with Kernel methods. Wiley.
Shajin, F., & Rajesh, P. (2020). Trusted secure geographic routing protocol: outsider attack detection in mobile ad hoc networks by adopting trusted secure geographic routing protocol. International Journal of Pervasive Computing and Communications. https://doi.org/10.1108/ijpcc-09-2020-0136
Sharma, I., Kumar, A., Balyan, L., & Singh, G. K. (2017). A new hybrid CSE technique for multiplier-less FIR filter. In Proceedings of the 2017 22nd International Conference on Digital Signal Processing (DSP) (pp. 1–5). IEEE.
Srinivasa Reddy, K., & Sahoo, S. K. (2017). An approach for fixed coefficient RNS-based FIR filter. International Journal of Electronics, 104(8), 1358–1376
Suhanova, K. A., & Serov, A. N. (2020). Application of simulink for simulation of the RMS measurement method based on low-pass filtration. In Proceedings of the 2020 International Russian Automation Conference (RusAutoCon) (pp. 571–576). IEEE.
Sumalatha, M., Naganjaneyulu, P. V., & Prasad, K. S. (2019). Low power and low area VLSI implementation of vedic design FIR filter for ECG signal de-noising. Microprocessors and Microsystems, 71, 102883
Tan, L. S., & Nott, D. J. (2018). Gaussian variational approximation with sparse precision matrices. Statistics and Computing, 28(2), 259–275.
Thota, M. K., Shajin, F. H., & Rajesh, P. (2020). Survey on software defect prediction techniques. International Journal of Applied Science and Engineering, 17, 331–344. https://doi.org/10.6703/IJASE.202012_17(4).331
Venkatachalam, S., & Ko, S. B. (2017). Design of power and area efficient approximate multipliers. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 25(5), 1782–1786.
Vinitha, C. S., & Sharma, R. K. (2020). Area and energy-efficient approximate distributive arithmetic architecture for LMS adaptive FIR filter. In Proceedings of the 2020 International Conference for Emerging Technology (INCET) (pp. 1–5). IEEE.
Wang, C. S., & Su, W. T. (2018). An efficient mobile AR navigation system using polygon approximation based data acquisition. In International Wireless Internet Conference (pp. 215–224). Springer, Cham.
Yan, W., Ercegovac, M. D., & Chen, H. (2016). An energy-efficient multiplier with fully overlapped partial products reduction and final addition. IEEE Transactions on Circuits and Systems I: Regular Papers, 63(11), 1954–1963
Zeng, A., Ho, H., & Yu, Y. (2020). Prediction of building electricity usage using Gaussian Process Regression. Journal of Building Engineering, 28, 101054
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Arumugam, N., Paramasivan, B. An integrated FIR adaptive filter design by hybridizing canonical signed digit (CSD) and approximate booth recode (ABR) algorithm in DA architecture for the reduction of noise in the sensor nodes. Multidim Syst Sign Process (2021). https://doi.org/10.1007/s11045-021-00783-y
- Finite impulse response (FIR)
- Distributed arithmetic (DA)
- Look-up tables (LUTs)
- Field programmable gate arrays (FPGA)
- Wallace tree and canonical signed digit (CSD) and Approximate booth recoder (ABR)