Multimedia Tools and Applications

, Volume 78, Issue 5, pp 5463–5478 | Cite as

A spill data aware memory assignment technique for improving power consumption of multimedia memory systems

  • Jonghee Youn
  • Doosan ChoEmail author


As embedded memory technology evolves, the traditional Static Random Access Memory (SRAM) technology has reached the end of development. For deepening the manufacturing process technology, the next generation memory technology is highly required because of the exponentially increasing leakage current of SRAM. Non-volatile memories such as STT-MRAM (Spin Torque Transfer Magnetic Random Access Memory), PCM (Phase Change Memory) are good candidates for replacing SRAM technology in embedded memory systems. They have many advanced characteristics in the perspective of power consumption, leakage power, size (density) and latency. Nonetheless, nonvolatile memories have two major problems that hinder their use it the next-generation memory. First, the lifetime of the nonvolatile memory cell is limited by the number of write operations. Next, the write operation consumes more latency and power than the same size of the read operation. This study describes a compiler optimization technique to overcome such disadvantages of a nonvolatile memory component in hybrid cache memories. A hybrid cache is proposed to overcome the disadvantages using a compiler. Specifically, to minimize the number of write operations for nonvolatile memory, we present a data replacement technique that considers the locations of the register spill data. Many portions of the memory accesses are yielded by the spill data of a register allocator in an optimizing compiler. Such spill data can be partially removed using a recalculation method. Thus, we implemented an optimization technique that rearranges the data placement with recalculation to minimize the write instructions on the nonvolatile memory. Our experimental results show that the proposed technique can reduce the average number of spill codes by 20%, and improves the energy consumption by 20.2% on average.


Multimedia application Energy consumption Hybrid cache Embedded system Nonvolatile memory Scratchpad memory 



This research was supported by the MSIT(Ministry of Science, ICT), Korea, under the ITRC(Information Technology Research Center) support program(IITP-2018-2016-0-00313) supervised by the IITP(Institute for Information & communications Technology Promotion), the National Research Foundation of Korea(NRF) grant funded by the Korea government (MSIT) (No.2018R1D1A1B0705647), and Basic Science Research Program through the National Research Foundation of Korea(NRF) funded by the Ministry of Education(NRF-2018R1D1A1B07050054), and the Yeungnam University Research Grant.


  1. 1.
    Briggs P (1992) Register Allocation via Graph Coloring. PhD thesis, Rice UniversityGoogle Scholar
  2. 2.
    Cho H, Egger B, Lee J, Shin H (2007) Dynamic data scratchpad memory management for a memory subsystem with an MMU. ACM LCTES: 13–15Google Scholar
  3. 3.
    Cho D, Pasricha S, Issenin I, Dutt N, Ahn M, Paek Y (2009) Adaptive scratch pad memory Management for Dynamic Behavior of multimedia applications. IEEE Trans Comput-Aided Design Integ Circ Syst 28(4):554–567CrossRefGoogle Scholar
  4. 4.
    Chu Y-S, Hsieh J-W, Chang Y-H, Kuo T-W (2009) A set-based mapping strategy for flash-memory reliability enhancement. DATE: 405–410Google Scholar
  5. 5.
    Dong X, Jouppi NP, Xie Y (2009) Pcramsim: system-level performance, energy, and area modeling for phase-change ram. Proc 2009 Int Conf Comput Aided Des: 269–275Google Scholar
  6. 6.
    Gebotys CH (1997) Low energy memory and register allocation using network flow. Proc 34th Ann Design Auto Conf: 435–440Google Scholar
  7. 7.
    Guthaus MR, Ringenberg JS, Ernst D, Austin TM, Mudge T, Brown RB (2001) Mibench: a free, commercially representative embedded benchmark suite. 2001 IEEE Int Workshop Workload Charact: 3–14Google Scholar
  8. 8.
    Hu J, Xue C, Tseng W, Zhuge Q, Sha EH-M (2010) Minimizing write activities to non-volatile memory via scheduling and recomputation. Proc 8th IEEE Sym Appl Specific Process: 7–12Google Scholar
  9. 9.
    Hu J, Xue C, Tseng W, He Y, Qiu M, Sha EH-M (2010) Reducing write activities on non-volatile memories in embedded CMPs via data migration and recomputation. Proc 47th IEEE/ACM Design Auto Conf: 350–355Google Scholar
  10. 10.
    Kang S, Dean AG (2012) Leveraging both data cache and scratchpad memory through synergetic data allocation. IEEE Real-Time Embed Technol Appl SymGoogle Scholar
  11. 11.
    Kennedy K (1978) Use-definition chains with applications. Comput Lang 3(3):163–179CrossRefGoogle Scholar
  12. 12.
    Lee B, Zhou P, Yang J, Zhang Y, Zhao B, Ipek E, Mutlu O, Burger D (2010) Phase-change technology and the future of Main memory. IEEE Micro 30:143CrossRefGoogle Scholar
  13. 13.
    M. Inc (2000) Motorola dsp 563000 family manual revision 3.0Google Scholar
  14. 14.
    Park C, Lim J, Kwon K, Lee J, Min SL (2004) Compiler-assisted demand paging for embedded systems with flash memory. Proc 4th ACM Int Conf Embed Softw: 114–124Google Scholar
  15. 15.
    Puhr-Westerheide (1979) Graphs of data flow dependencies. IFAC Proc 12(1):117–127CrossRefGoogle Scholar
  16. 16.
    Rodríguez G, Touriño J, Kandemir MT (2015) Volatile STT-RAM scratchpad design and data allocation for low energy. ACM Trans Architect Code Optim (TACO) 11(4):1–26Google Scholar
  17. 17.
    Shi L, Xue C, Hu J, Tseng W, Sha EH-M (2010) Write activity reduction on flash main memory via smart victim cache. Proc ACM/IEEE 20th Great Lakes Sym VLSI : 91–94Google Scholar
  18. 18.
    Thammanur S, Pande S (2004) A Fast Memory-efficient Register allocation framework for embedded systems. ACM Trans Program Lang Syst: 938–974CrossRefGoogle Scholar
  19. 19.
    Wu Y, Larus JR (1994) Static branch frequency and program profile analysis. Proc 27th Ann Int Sym Microarchitect: 1–11Google Scholar
  20. 20.
    Zhou P, Zhao B, Yang J, Zhang Y-T (2009) A durable and energy efficient Main memory using phase change memory technology. Comput Architect News: 14–23CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Computer EngineeringYeungnam UniversityGyeongsanSouth Korea
  2. 2.Department of Electrical and Electronic EngineeringSunchon National UniversitySuncheonSouth Korea

Personalised recommendations