Multimedia Tools and Applications

, Volume 77, Issue 20, pp 26793–26819 | Cite as

An ASIC based invisible watermarking of grayscale images using pixel value search algorithm (PVSA)

  • S. M. Sakthivel
  • A. Ravi SankarEmail author


Digital image watermarking has become more popular due to its applications in copyright protection and secret communication. Most of the image watermarking algorithms reported till date involve modification of the host contents for embedding a secret data, leading to a reduced robustness and a limited embedding capacity. In the present work, a novel spatial domain watermarking scheme called Pixel Value Search Algorithm (PVSA) is proposed using a linear search operation to achieve high robustness and a theoretically unlimited embedding capacity. In the proposed scheme, secret data are embedded into a host image by mapping their intensity values into row and column locations. Due to this linear mapping of secret data, the host structural content is not altered. In addition, multiple watermarks can be mapped into a single host image using the PVSA technique. The proposed algorithm is verified using MATLAB® simulations and its performance characteristics are assessed using a standard benchmark tool called strimark. Experimental results illustrate the robustness of the PVSA technique against the attacks of Gaussian blurring, Gaussian noise, salt and pepper noise, Poisson noise, speckle noise, mean and median filtering, histogram equalization, image sharpening, intensity transformation, unsharp filtering, JPEG attack, etc. Subsequently an ASIC implementation of the PVSA algorithm is carried out using Verilog HDL and various modules of the Cadence® EDA tool so as to integrate the chip as a watermark co-processor. The ASIC implementation using a 0.18 μm technology at an operating frequency of 100 MHz consumes a power of 326.34 μW for the complete hardware architecture.


Real time image watermarking VLSI datapath architecture ASIC chip Watermarking co-processor PVSA algorithm Stirmark tool 


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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.School of Electronics Engineering (SENSE)Vellore Institute of Technology (VIT)ChennaiIndia

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