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Computation Hierarchy for In-Network Processing

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Abstract

In this paper we explore the network level architecture of distributed sensor systems that perform in-network processing. We propose a system with heterogeneous nodes that organizes into a hierarchical structure dictated by the computational capabilities. The presence of high-performance nodes amongst a sea of resource-constrained nodes exposes new tradeoffs for the efficient implementation of network-wide applications. Our experiments show that even for a low relative density of resource-constrained nodes to high-performance nodes there are certain gains in performance for a heterogeneous and hierarchical network over a homogeneous one. The introduction of hierarchy enables partitioning of the application into sub-tasks that can be mapped onto the heterogeneous nodes in the network in multiple ways. We analyze the tradeoffs between the execution time of the application, accuracy of the output produced and the overall energy consumption of the network for the different mapping of the sub-tasks onto the heterogeneous nodes. We evaluate the performance and energy consumption of a typical sensor network application of target tracking via beamforming and line of bearing (LOB) calculations on the different nodes. Our experiments also include the study of the overall performance and energy consumption of the LOB calculation using two different types of resource constrained sensor nodes (MICA and MICA2 nodes) and show how these metrics are affected by changes in the node architecture and operation. Our results indicate that when using MICA motes as resource-constrained nodes, 85% of the time on average the hierarchical network outperforms a homogeneous network for approximately the same energy budget. When using MICA2 motes as resource-constrained nodes, 54% of the time the hierarchical network performs better than a homogeneous network with approximately the same energy budget.

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Authors and Affiliations

  1. Networked & Embedded Systems Lab, Electrical Engineering Dept., UCLA, LA, Boelter Hall 1762, CA, 90095, USA

    Vlasios Tsiatsis, Ram Kumar & Mani B. Srivastava

Authors
  1. Vlasios Tsiatsis
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  2. Ram Kumar
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  3. Mani B. Srivastava
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Correspondence to Vlasios Tsiatsis.

Additional information

Vlasios Tsiatsis received the BS degree from the Technical University of Crete, Chania, Greece, in 1998, and the MS degree in Electrical Engineering from the University of California, Los Angeles (UCLA), in 2001. He is currently pursuing a PhD degree at UCLA. His research interests include low-power protocol and system design in heterogeneous sensor networks.

Ram Kumar is a PhD student in the Electrical Engineering department at UCLA. He received his MS degree from the same department in 2003, and his B.S. degree from the Indian Institute of Technology, Delhi in 2001. His current research interests focus on programming techniques for distributed ad-hoc sensor networks and architectures of heterogeneous networks of sensors.

Mani Srivastava (Ph.D., U.C. Berkeley, 1992; M.S., U.C. Berkeley, 1987, and B.Tech., IIT Kanpur, 1985) is Professor at UCLA’s Electrical Engineering Department and the Center for Embedded Networked Sensing. His research is on various technology, fundamental, and application aspects of networked embedded systems such as wireless sensor/actuator networks. Prior to joining the faculty at UCLA he worked at Bell Labs Research in the area of Networked Computing. Among the awards that he has received are the President of India’s Gold Medal, the NSF CAREER Award, and the Okawa Foundation Grant. More information about him and his research group is available at http://nesl.ee.ucla.edu.

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Tsiatsis, V., Kumar, R. & Srivastava, M.B. Computation Hierarchy for In-Network Processing. Mobile Netw Appl 10, 505–518 (2005). https://doi.org/10.1007/s11036-005-1563-z

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