A combined procedural and hardware complex of electrophysical methods for management of submicrometric CMOS integrated circuit technology is developed and implemented. Programmable switching of the elements of the complex that makes it possible to utilize a mutually complementary measurement technique to obtain information needed to correct the production process is created. The complex includes programs to control the measurement and calculation of required characteristics.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
P. J. McWhorter and P. S. Winokur, “Simple technique for separating the effects of interface traps and trapped-oxide charge in metal-oxide-semiconductor transistors,” Appl. Phys. Lett., 48, No. 2, 133–135 (1986).
G. Groeseneken, H. E. Maes, N. Beltrain, and R. F. de Keersmaecker, “A reliable approach to charge-pumping measurements in MOS transistors,” IEEE Trans. ED, 31, 42–53 (1984).
I. Starkover, S. Enichlmair, S. Tyaginov, and T. Grasser, “Charge-pumping extraction techniques for hot-carrier induced interface and oxide trap spatial distributions in MOSFGETs,” in: 19th IEEE Int. Symp., IPFA (2012), pp. 1–6.
C. Chen and T.-P. Ma, “Direct lateral profiling in hot-carrier-induced oxide charge and interface traps in thin gate MOSFETs,” IEEE Trans. ED, 45, No. 2, 512–520 (1998).
K. G. Popovskikh, E. V. Zenova, A. M. Tagachenkov, and V. S. Soldatov, “Comparative study of gate systems of n-and p-channel KMDP VLSI MDS transistors by electrophysical methods,” in: Fluctuation and Degradation Processes in Semiconductor Devices: Proc. Sci. Seminar, MNTORES im. Popova, NIU MEI, Moscow (2015), pp. 123–130.
K. G. Popovskikh, K. G. Oreshkov, and V. S. Soldatov, “Diagnostics of charged gate system of KMDP VLSI MDS transistors under different types of stress by the charge pumping method,” ibid., pp. 120–138.
R. G.-H. Lee, J.-S. Su, and S. S. Chung, “A new method for characterizing the spatial distributions of interface states and oxide-trapped charges in LDD n-MOSFETs,” IEEE Trans. ED, 43, No. 1, 81–89 (1996).
T. Hori, Gate Dielectrics and MOS ULSIs, Springer-Verlag, Berlin/Heidelberg (1997).
T. Y. Chang, J. Chen, P. K. Ko, and C. Hu, “The impact of gate-induced drain leakage current on MOSFET scaling,” IEEE IEDM Digest (1987), pp. 718–721.
T. Hori, “Drain-structure design for reduced band-to-band and band-to-defect tunneling leakage,” IEEE Symp. VLSI Technol. Digest (1990), pp. 69–70.
R. Degraeve, G. Groeseneken, R. Bellens, et al., “New insights in the relation between electron trap generation and the statistical properties of oxide breakdown,” IEEE Trans. ED, 45, No. 4, 904–911(1998).
Author information
Authors and Affiliations
Corresponding author
Additional information
Translated from Izmeritel’naya Tekhnika, No. 9, pp. 3–7, September, 2016.
Rights and permissions
About this article
Cite this article
Popovskikh, K.G., Soldatov, V.S. & Oreshkov, M.V. Hardware/Software Complex for Electrophysical Management of CMOS Technology on Test Structures. Meas Tech 59, 904–910 (2016). https://doi.org/10.1007/s11018-016-1065-3
Received:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s11018-016-1065-3