Abstract
Single-pixel prototype superconductor–insulator–superconductor (SIS) mixer integrated circuits (ICs) for multi-beam heterodyne receivers were fabricated. We introduced plasma-enhanced chemical vapor deposition (PE-CVD) for insulator layer deposition and machine-aligned via-hole etching for contact-hole definition on SIS junctions to achieve high uniformity and yield. In the PE-CVD, we applied a compressive/tensile/compressive SiO2 trilayer technique to control the film stress. The SiO2 trilayer stress was stable and negligibly low. The uniformity and junction quality yield of the single-pixel prototype SIS mixer ICs were improved in the process applying the PE-CVD and the via-hole etching.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
J. C. Webber, in Proceedings of IEEE MTT-S International Microwave Symposium Digest (MTT), pp. 1–3 (2013). https://doi.org/10.1109/mwsym.2013.6697433
K. Akiyama et al., Astrophys. J. Lett. 875, L1 (2019). https://doi.org/10.3847/2041-8213/ab0ec7
N. Nakai, M. Inoue, M. Miyoshi, Nature 361, 45–47 (1993). https://doi.org/10.1038/361045a0
T. Nagao et al., Astron. Astrophys. 542, L34 (2012). https://doi.org/10.1051/0004-6361/201219518
T. Hashimoto et al., Nature 557, 392–395 (2018). https://doi.org/10.1038/s41586-018-0117-z
R. Adam et al., Astron. Astrophys. 609, A115 (2018). https://doi.org/10.1051/0004-6361/201731503
W.S. Holland et al., Monthly Notices Roy. Astron. Soc. 430(4), 2513–2533 (2013). https://doi.org/10.1093/mnras/sts612
W. Shan et al., IEEE Trans. Terahertz Sci. Technol. 8(4), 472–474 (2018). https://doi.org/10.1109/TTHZ.2018.2842750
W. Shan et al., Proc. SPIE 10708, 1070814 (2018). https://doi.org/10.1117/12.2311933
S. Ezaki et al., IEEE Trans. Appl. Supercond. 29(5), 1101405 (2019). https://doi.org/10.1109/TASC.2019.2902985
X. Meng, A. Bhat, T. van Duzer, IEEE Trans. Appl. Supercond. 9(2), 3208–3211 (1999). https://doi.org/10.1109/77.783711
T. Lehnert et al., J. Appl. Phys. 72(7), 3165–3168 (1992). https://doi.org/10.1063/1.351479
D. Dochev et al., J. Phys: Conf. Ser. 234, 042006 (2010). https://doi.org/10.1088/1742-6596/234/4/042006
M.S. Haque, H.A. Naseem, W.D. Brown, Thin Solid Films 308, 68–73 (1997). https://doi.org/10.1016/S0040-6090(97)00542-7
S. Morohashi, S. Hasuo, T. Yamaoka, Appl. Phys. Lett. 48, 254 (1986). https://doi.org/10.1063/1.96573
A. Endo et al., IEEE Trans. Appl. Supercond. 19(3), 400–404 (2009). https://doi.org/10.1109/tasc.2009.2019053
P.N. Dmitriev et al., IEEE Trans. Appl. Supercond. 9(2), 3970–3973 (1999). https://doi.org/10.1109/77.783897
Acknowledgements
The authors are grateful to Akihira Miyachi and Matthias Kroug of NAOJ for their input on the fabrication processes. This work was supported in part by the Japan Society for the Promotion of Science KAKENHI under Grant Number 18K03708.
Author information
Authors and Affiliations
Corresponding author
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Ezaki, S., Shan, W. & Uzawa, Y. Fabrication of Planar-Integrated SIS Mixer Circuits with Improved Uniformity and Yield. J Low Temp Phys 199, 369–375 (2020). https://doi.org/10.1007/s10909-020-02433-2
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10909-020-02433-2