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The Role of the Gate Geometry for Cryogenic HEMTs: Towards an Input Voltage Noise Below \(0.5~\mathrm{nV}/\sqrt{\mathrm{Hz}}\) at 1 kHz and 4.2 K

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Abstract

Specific HEMTs (High Electron Mobility Transistors) with different gate geometries have been realized on the same AlGaAs/GaAs heterojunction. Under the same operating conditions with a power consumption of 30 μW, experimental results at 4.2 K and low frequency range show that the input voltage noise is almost inversely proportional to the square root of the input capacitance: a noise value as low as \(0.46~\mathrm{nV}/\sqrt{\mathrm{Hz}}\) at 1 kHz has been obtained with an input capacitance of about 100 pF.

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Acknowledgements

This work was supported in part by the Réseau RENATECH, “le RTRA Triangle de la Physique” grants No. 2008-015T and No. 2009-004T and European FP7 grant No. 263455. Q.D. is funded by the BDI CNRS/CEA. We acknowledge stimulating discussions with H. Bouchiat, D.C. Glattli, C. Pigot, F. Pierre and A. Anthore. We thank E. Cambril and L. Couraud for technical help.

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  1. Laboratoire de Photonique et de Nanostructures, CNRS, Route de Nozay, 91460, Marcoussis, France

    Q. Dong, Y. X. Liang, U. Gennser, A. Cavanna & Y. Jin

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  1. Q. Dong
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  2. Y. X. Liang
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  3. U. Gennser
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  4. A. Cavanna
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  5. Y. Jin
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Correspondence to Y. Jin.

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Dong, Q., Liang, Y.X., Gennser, U. et al. The Role of the Gate Geometry for Cryogenic HEMTs: Towards an Input Voltage Noise Below \(0.5~\mathrm{nV}/\sqrt{\mathrm{Hz}}\) at 1 kHz and 4.2 K. J Low Temp Phys 167, 626–631 (2012). https://doi.org/10.1007/s10909-012-0459-0

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  • DOI: https://doi.org/10.1007/s10909-012-0459-0

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