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Race to idle or not: balancing the memory sleep time with DVS for energy minimization

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Abstract

Reducing energy consumption is a critical problem in most of the computing systems today. Among all the computing system components, processor and memory are two significant energy consumers. Dynamic voltage scaling is typically applied to reduce processor energy while sleep mode is usually injected to trim memory’s leakage energy. However, in the memory architecture with multiple cores sharing memory, in order to optimize the system-wide energy, these two classic techniques are difficult to be directly combined due to the complicated interactions. In this work, we explore the coordination of the multiple cores and the memory, and present systematic analysis for minimizing the system-wide energy based on different system models and task models. For tasks with common release time, optimal schemes are presented for the systems both with and without considering the static power of the cores. For agreeable deadline tasks, different dynamic programming-based optimal solutions are proposed for negligible and non-negligible static power of cores. For the general task model, this paper proposes a heuristic online algorithm. Furthermore, the scheme is extended to handle the problem when the transition overhead between the active and sleep modes is considered. The optimality of the proposed schemes for common release time and agreeable deadline tasks are proved. The validity of the proposed heuristic scheme is evaluated through experiments. Experimental results confirm the superiority of the heuristic scheme in terms of the energy saving improvement compared to the most related existing work.

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Acknowledgements

The work described in this paper was partly supported by grants from the Research Grants Council of the Hong Kong Special Administrative Region, China [Project No. CityU 117913] and [Project No. CityU 11278316].

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Authors and Affiliations

  1. Department of Computer Science, City University of Hong Kong, Hong Kong SAR, China

    Chenchen Fu, Vincent Chau, Minming Li & Chun Jason Xue

  2. Shenzhen Institutes of Advanced Technology, Shenzhen, China

    Vincent Chau

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  1. Chenchen Fu
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  2. Vincent Chau
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  3. Minming Li
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  4. Chun Jason Xue
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Correspondence to Vincent Chau.

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Fu, C., Chau, V., Li, M. et al. Race to idle or not: balancing the memory sleep time with DVS for energy minimization. J Comb Optim 35, 860–894 (2018). https://doi.org/10.1007/s10878-017-0229-7

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