Abstract
Discrete gate sizing is a critical optimization in VLSI circuit design. Given a set of available gate sizes, discrete gate sizing problem asks to assign a size to each gate such that the delay of a combinational circuit is minimized while the cost constraint is satisfied. It is one of the most studied problems in VLSI computer-aided design. Despite this, all of the existing techniques are heuristics with no performance guarantee. This limits the understanding of the discrete gate sizing problem in theory.
This paper designs the first fully polynomial time approximation scheme (FPTAS) for the delay driven discrete gate sizing problem. The proposed approximation scheme involves a level based dynamic programming algorithm which handles the specific structures of a discrete gate sizing problem and adopts an efficient oracle query procedure. It can approximate the optimal gate sizing solution within a factor of (1+ε) in O(n 1+c m 3c/ε c) time for 0<ε<1 and in O(n 1+c m 3c) time for ε≥1, where n is the number of gates, m is the maximum number of gate sizes for any gate, and c is the maximum number of gates per level. The FPTAS needs the assumption that c is a constant and thus it is an approximation algorithm for the restricted discrete gate sizing problem.
This is a preview of subscription content, log in via an institution to check access.
Similar content being viewed by others
References
Beeftink F, Kudva P, Kung D, Stok L (1998) Gate size selection for standard cell libraries. In: Proceedings of IEEE/ACM international conference on computer-aided design, pp 545–550
Berkelaar M, Jess J (1990) Gate sizing in mos digital circuits with linear programming. In: Proceedings of the European conference on design automation, pp 217–221
Bhattacharya K, Ranganathan N (2008) A linear programming formulation for security-aware gate sizing. In: Proceedings of ACM great lakes symposium on VLSI, pp 273–278
Chen C-P, Chu C, Wong D (1999) Fast and exact simultaneous gate and wire sizing by Lagrangian relaxation. IEEE Trans Comput-Aided Des Integr Circuits Syst 18(7):101–1025
Chuang W, Sapatnekar SS, Hajj IN (1995) Timing and area optimization for standard-cell VLSI circuit design. IEEE Trans Comput-Aided Des Integr Circuits Syst 14(3):308–320
Coudert O (1997) Gate sizing for constrained delay/power/area. IEEE Trans Very Large Scale Integr (VLSI) Syst 5(4):465–472
Elmore WC (1948) The transient analysis of damped linear networks with particular regard to wideband amplifiers. J Appl Phys 19(1):321–336
Ergun F, Sinha R, Zhang L (2002) An improved FPTAS for restricted shortest path. Inf Process Lett 83(5):287–291
Fishburn J, Dunlop A (1985) Tilos: a posynomial programming approach to transistor sizing. In: Proceedings of IEEE/ACM international conference on computer-aided design, pp 326–328
Hanchate N, Ranganathan N (2006) Simultaneous interconnect delay and crosstalk noise optimization through gate sizing using game theory. IEEE Trans Comput 55(8):1011–1023
Hassin R (1992) Approximation schemes for the restricted shortest path problem. Math Oper Res 17(1):36–42
Hu S, Ketkar M, Hu J (2007) Gate sizing for cell library-based designs. In: Proceedings of ACM/IEEE design automation conference, pp 847–852
Hu S, Li Z, Alpert C (2009a) A fully polynomial time approximation scheme for timing driven minimum cost buffer insertion. In: Proceedings of ACM/IEEE design automation conference (DAC)
Hu S, Li Z, Alpert C (2009b) A faster approximation scheme for timing driven minimum cost layer assignment. In: Proceedings of ACM international symposium on physical design (ISPD)
Mahalingam V, Ranganathan N, Harlow J III (2006) A novel approach for variation aware power minimization during gate sizing. In: Proceedings of international symposium on low power electronics and design, pp 174–179
Mani M, Orshansky M (2004) A new statistical optimization algorithm for gate sizing. In: Proceedings of international conference on computer design, pp 272–277
Murugavel A, Ranganathan N (2004) Gate sizing and buffer insertion using economic models for power optimization. In: Proceedings of IEEE international conference on VLSI design, pp 195–200
Ning W (1994) Strongly NP-hard discrete gate-sizing problems. IEEE Trans Comput-Aided Des Integr Circuits Syst 13(8):1045–1051
Ren H, Dutt S (2008) A network-flow based cell sizing algorithm. In: Proceedings of international workshop on logic synthesis, pp 7–14
Sapatnekar S, Rao V, Vaidya P (1993) An exact solution to the transistor sizing problem for CMOS circuits using convex optimization. IEEE Trans Comput-Aided Des Integr Circuits Syst 12(11):1621–1634
Singh J, Nookala V, Luo Z, Sapatnekar S (2005) Robust gate sizing by geometric programming. In: Proceedings of ACM/IEEE design automation conference, pp 315–320
Sinha D, Zhou H (2004) Gate sizing for crosstalk reduction under timing constraints by Lagrangian relaxation. In: Proceedings of IEEE/ACM international conference on computer-aided design, pp 14–19
Sundararajan V, Sapatnekar SS, Parhi KK (2002) Fast and exact transistor sizing based on iterative relaxation. IEEE Trans Comput-Aided Des Integr Circuits Systems 21(5):568–581
Tennakoon H, Sechen C (2002) Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. In: Proceedings of IEEE/ACM international conference on computer-aided design, pp 395–402
Vazirani VV (2001) Approximation algorithms. Springer, Berlin
Wang J, Das D, Zhou H (2007) Gate sizing by Lagrangian relaxation revisited. In: Proceedings of IEEE/ACM international conference on computer-aided design, pp 111–118
Wu T-H, Xie L, Davoodi A (2008) A parallel and randomized algorithm for large-scale discrete dual-Vt assignment and continuous gate sizing. In: Proceedings of international symposium on low power electronics and design, pp 45–50
Zhou Q, Mohanram K (2006) Gate sizing to radiation harden combinational logic. IEEE Trans Comput-Aided Desi Integr Circuits Syst 25(1):155–166
Kasamsetty K, Ketkar M, Sapatnekar SS (2000) A new class of convex functions for delay modeling and their application to the transistor sizing problem. IEEE Trans Comput-Aided Des Integr Circuits Syst 19(7):779–788
Ketkar M, Kasamsetty K, Sapatnekar SS (2000) Convex delay models for transistor sizing. In: Proceedings of the ACM/IEEE design automation conference, pp 655–660
Roy S, Chen W, Chen CC, Hu Y (2007) Numerically convex forms and their application in gate-sizing. IEEE Trans Comput-Aided Des Integr Circuits Syst (TCAD) 26(9):1637–1647
Xie L, Davoodi A (2008) Fast and accurate statistical static timing analysis with skewed process parameter variation. In: Proceedings of ACM/IEEE international symposium on quality electronic design (ISQED’08), pp 712–717
Author information
Authors and Affiliations
Corresponding author
Rights and permissions
About this article
Cite this article
Liao, C., Hu, S. Approximation scheme for restricted discrete gate sizing targeting delay minimization. J Comb Optim 21, 497–510 (2011). https://doi.org/10.1007/s10878-009-9267-0
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10878-009-9267-0