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Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package

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Abstract

The increasing demand over the higher density and smaller form factor of memory packages have become a mainstream due to the boom of artificial intelligence and 5G/6G. While form factor of memory packages moves toward smaller and thinner geometry with higher pin counts, the package overall thermal–mechanical behavior is one of a key concern due to the harsh environment of field usage. In the paper, solder joint reliability test is conducted to understand the thermal–mechanical performance between the direct chip-attach (DCA) and fan-out chip scale package (FOCSP). It is observed the overall reliability of DCA package performs better than FOCSP, which is likely because of coefficient of thermal expansion (CTE) mismatch. Inside the FOCSP structure, the results indicate that higher Cu stud height and thinner base die thickness would contribute to better reliability performance. In failure analysis, the failure modes of signal and power net inside FOCSP packages occur either at Cu RDL (Redistribution Layers) crack or IMC (Interface Metallic Compound)/solder crack. In terms of DCA package, the signal net is likely to occur slight electrical short, and the power net exhibit the IMC/solder crack near package side. In addition, the thermal interface analysis of warpage behavior between PCB and package has been studied to correlate with the solder joint reliability performance inside FOCSP case. In thermal warpage analysis of DCA package and board, when under colling stage profile, the package sits at center location exhibit more thermal stress then the edge one, shifting JFFS warpage from negative to positive value, and thus lead to earlier failure. Last, the study will list out a table to discuss the pros and cons of DCA and FOCSP package in terms of reliability, cost, and signal integrity perspective.

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Data availability

The datasets generated during and/or analyzed during the current study are available from the corresponding author on reasonable request.

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Acknowledgements

Despite multiple challenges in the progress of this project, the author would like to pay sincere gratefulness to all PDE members, Micron Technology Inc., who make this project possible.

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Micron Technology, 0000443159, Vance Liu

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Authors and Affiliations

  1. Package Development Department, Material Characterization & Reliability Group, Micron Technology Inc., Taichung City, 42152, Taiwan

    Vance Liu, Chia-Tien Chen, Yi-Jing Chen, Yi-Yu Chen, Chien-Ming Chen & Chong Leong Gan

  2. Global Quality Department, Ackage Qual& Reliability Group, Micron Technology Inc., Taichung City, 42152, Taiwan

    Richard Fan

  3. Package Simulation Group, Package Development Department, Micron Technology Inc., Boise, ID, 83707, USA

    Koustav Sinha

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All authors whose names appear on the submission made substantial contributions to the conception or design of the work, analysis, interpretation of data, drafted the work, and revised it critically for important intellectual content. All authors approve the version to be published and agree to be accountable for all aspects of the work in ensuring that questions related to the accuracy or integrity of any part of the work are appropriately investigated and resolved.

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Correspondence to Vance Liu or Koustav Sinha.

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Vance Liu reports financial support was provided by Micron Technology Inc. Vance Liu reports a relationship with Micron Technology Inc. that includes employment and funding grants. Author and co-authors are all currently employed in Micron Technology Inc.

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Liu, V., Sinha, K., Chen, CT. et al. Comparative study of solder joint reliability assessment on fan-out CSP and flip-chip DCA package. J Mater Sci: Mater Electron 34, 2130 (2023). https://doi.org/10.1007/s10854-023-11546-9

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