Abstract
This paper describes a junctionless double-gate FET at nanoscale dimensions that utilizes a ß-Ga2O3 packet to improve and amend the electric field at the device's beginning and in the channel. The fundamental concept behind this design is to place a ß-Ga2O3 packet at the intersection of the source and channel devices. The distribution of the electric field inside the device is amended and the peak of the electric field in the channel area is altered as a result of the characteristics of the ß-Ga2O3 material. Additionally, the electric field's modification has lowered the structure's temperature and improved the carrier's mobility. Also, the performance of the proposed device exhibits an improvement in the short-channel effect. The use of this packet has a significant impact on the device's performance, improving both AC and DC properties in the proposed device. The proposed device's simulation results demonstrate a significant improvement in the features of the lattice temperature, electron mobility, leakage current, hole concentration, drain-induced barrier lowering (DIBL), and subthreshold slope. Additionally, compared to a conventional structure, the AC properties, such as noise and unilateral power gain, as well as the sum of the gate-source and gate-drain capacitors, showed a considerable improvement.
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M. Heidari contributed to conceptualization, writing—original draft, and software. A. A. Orouji contributed to supervision—review & editing. S. A. Bozorgi contributed to validation, review & editing.
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Heidari, M., Orouji, A.A. & Bozorgi, S.A. A nanoscale junctionless FET to amend the electric field distribution using a β-Ga2O3 packet. J Mater Sci: Mater Electron 34, 1708 (2023). https://doi.org/10.1007/s10854-023-11104-3
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DOI: https://doi.org/10.1007/s10854-023-11104-3