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SiGe Fin field effect transistor (FET) with STI liner skipping and channel passivation engineering

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Abstract

In this paper, shallow trench isolation (STI) liner layer skipping and channel passivation engineering for the SiGe channel FinFET device are investigated in detail. First, to skip the STI liner layer and simplify the integration process, an optimized rapid thermal annealing (RTA) STI densification annealing of 850 °C for 30 s in N2 ambient is developed. And a high quality and thermal stable SiGe fin under STI last strategy can be successfully prepared. Then, combined with the stacked HfO2/Al2O3 gate dielectric, the SiGe film is directly ozone passivated at 300 °C for 30 min to improve its interface quality. As a result, a low interface state density of 4.8 × 1012 eV−1 cm−2 @ E − Ev = 0.33 eV is achieved. Finally, a SiGe channel FinFET device is successfully fabricated utilizing these newly developed processes. In particular, compared with unoptimized SiGe FinFET device, its subthreshold slope can be improved from 149 to 89 mV/dec, which is a key index for the high-quality SiGe fin with improved interface quality. The above results confirm that the STI liner skipping engineering with an optimized RTA STI dentification annealing and the channel passivation engineering can be practicable technologies for the SiGe FinFET device.

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Data availability

The data that support the findings of this study are available from the corresponding author upon reasonable request.

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Acknowledgements

This work is supported by the Beijing Municipal Natural Science Foundation (Grant no. 4202078).

Funding

Beijing Municipal Natural Science Foundation, 4202078, Yongliang Li

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Authors and Affiliations

  1. Integrated Circuit Advanced Process Center, Institute of Microelectronics, Chinese Academy of Science, Beijing, 100029, People’s Republic of China

    Chun Li, Yongliang Li, Anlan Chen, Fei Zhao, Jun Luo & Wenwu Wang

  2. School of Integrated Circuits, University of Chinse Academy of Sciences, Beijing, 100049, People’s Republic of China

    Chun Li, Anlan Chen, Fei Zhao, Jun Luo & Wenwu Wang

Authors
  1. Chun Li
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  2. Yongliang Li
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  3. Anlan Chen
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  4. Fei Zhao
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  5. Jun Luo
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  6. Wenwu Wang
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Contributions

Conceptualization, methodology, and formal analysis: CL and YL, validation: FZ, writing—original draft preparation: CL and AC, writing—review and editing, JL and WW. All authors have read and agreed to the published version of the manuscript.

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Correspondence to Yongliang Li.

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Li, C., Li, Y., Chen, A. et al. SiGe Fin field effect transistor (FET) with STI liner skipping and channel passivation engineering. J Mater Sci: Mater Electron 34, 520 (2023). https://doi.org/10.1007/s10854-023-09945-z

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