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Gate modeling of metal–insulator–semiconductor devices based on ultra-thin atomic-layer deposited TiO2

Abstract

Metal–insulator–semiconductor devices having different oxide thicknesses (10, 6, 4 and 2 nm) were fabricated using atomic-layer deposited ultra-thin amorphous TiO2 as gate dielectric. From Ig–Vg measurements it was determined that the main conduction mechanism is Schottky emission for all thicknesses and even after passivation of the semiconductor–insulator interface using SiOx. Furthermore, the Schottky barrier height (ΦB) increases when the oxide thickness decreases; this was further corroborated using semi empirical models and SILVACO simulations having excellent agreement. From this analysis, important physical parameters like barrier height (ΦB), effective mass (m*) and optical dielectric constant (εr) were extracted, and could be used to effectively understand the performance and reliability of these devices. From the extraction of physical parameters associated to the conduction mechanism, a correlation between materials’ properties with device performance could be obtained (higher barrier height (ΦB) would result in a decrease in leakage current). Also, the high reproducibility enables enhanced performance and therefore, better reliability predictions for electron devices based on these oxides.

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Acknowledgements

This work was fully supported by the Mexican Council for Science and Technology (CONACYT-Mexico).

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Correspondence to Hector Uribe-Vargas.

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Uribe-Vargas, H., Molina-Reyes, J., Romero-Morán, A. et al. Gate modeling of metal–insulator–semiconductor devices based on ultra-thin atomic-layer deposited TiO2. J Mater Sci: Mater Electron 29, 15761–15769 (2018). https://doi.org/10.1007/s10854-018-9240-8

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