Understanding of post deposition annealing and substrate temperature effects on structural and electrical properties of Gd₂O₃ MOS capacitor

Abstract

The purpose of this study is to understand the effects of substrate temperature (ST) and post deposition annealing (PDA) on the structural-electrical properties of Gd₂O₃ film and to evaluate the electrical performances of the MOS based devices formed with this dielectric. The Gd₂O₃/Si structures were annealed at 500, 600, 700, and 800 °C under N₂ ambient after the films were grown on heated p-Si substrate at various temperatures ranged from 20 to 300 °C by RF magnetron sputtering. For any given ST, the crystallization/grain size increased with increasing PDA temperature. The bump in the accumulation region or continuous decrease in the capacitance values of the inversion region of the C–V curves for 800 °C PDA was not observed. The lowest effective oxide charge density (Q_eff) value was obtained to be − 1.13 × 10¹¹ cm⁻² from the MOS capacitor with Gd₂O₃, which is grown on heated Si at 300 °C and annealed at 800 °C. The density of the interface states (D_it) was found to be in the range of 0.84 × 10¹¹ to 1.50 × 10¹¹ eV⁻¹ cm⁻². The highest dielectric constant (ε) and barrier height $({\Phi _B})$ values were found to be 14.46 and 3.68, which are obtained for 20 °C ST and 800 °C PDA. The results show that the negative charge trapping in the oxide layer is generally more than that of the positive, but, it is reverse of this situation at the interface. The leakage current density decreased after 20 °C ST, but no significant change was observed for other ST values.