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Could application of column-grid-array (CGA) technology result in inelastic-strain-free state-of-stress in solder material?


Physically meaningful and easy-to-use analytical stress model is developed for a short cylinder (beam) clamped at the ends and subjected to bending caused by the ends offset. The offset is due, in its turn, to an external lateral force that has to be determined from the known offset. It is envisioned that such a beam can adequately represent the state of stress in a column-grid-array (CGA) solder joint interconnection experiencing thermal loading due to the thermal expansion/contraction mismatch of the IC package and the printed circuit board (PCB). The CGA designs are characterized by considerably higher stand-off heights than ball-grid-array (BGA) systems. The offset Δ = lΔαΔt for a CGA solder joint located at the distance l from the mid-cross-section of the package/PCB assembly (the neutral point (DNP)), can be determined, in an approximate analysis, as a product of this distance and the “external” thermal mismatch strain ΔαΔt between the IC package and the printed circuit board (PCB). Here Δα is the difference in the effective coefficients of thermal expansion (CTE) of the PCB and package materials, and Δt is the change in temperature. The objective of the analysis is to demonstrate that the application of a CGA design, in which the solder joints are configured as short clamped–clamped beams, enables one not only to significantly relieve the thermally induced stresses, compared to the BGA system, but possibly to do that to an extent that the stresses in the solder material would remain within the elastic range. If this is achieved, the low-cycle-fatigue condition for the solder material will be replaced by the elastic-fatigue condition, thereby leading to a significantly longer fatigue lifetime of the joint. The elastic fatigue lifetime can be assessed, as is known, based on the Palmgren–Miner rule of linear accumulation of damages. Our analysis is limited therefore to elastic deformations.

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Part of the research described in this paper was conducted at the Jet Propulsion Laboratory, California Institute of Technology, under a contract with the National Aeronautics and Space Administration. The second author would like to acknowledge also the JPL and industry supports. The author also extends his appreciation to program managers of NASA Electronic Parts and Packaging (NEPP) Program.

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Correspondence to Ephraim Suhir.

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Suhir, E., Ghaffarian, R. & Nicolics, J. Could application of column-grid-array (CGA) technology result in inelastic-strain-free state-of-stress in solder material?. J Mater Sci: Mater Electron 26, 10062–10067 (2015).

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  • Solder Joint
  • Print Circuit Board
  • Lateral Force
  • Inelastic Strain
  • Solder Material