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Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit

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Abstract

Resistive random-access memory (ReRAM) has several attractive features such as high storage density and high switching frequency with low power consumption. It is hence regarded as the most promising nonvolatile memory material. However, a memristor, which is a primitive component of the ReRAM-based memory, has much lower write endurance. Hence, an error-correcting code (ECC) circuit is indispensable for realizing reliable ReRAM storage. Accordingly, we propose a hybrid CMOS/memristor-based ECC circuit. In the proposed circuit, the blocks with high-frequency write operations are implemented using the conventional CMOS technology and the other blocks are implemented using the memristors to maintain a balance between the area overhead and reliability. Through numerical experiments, we demonstrate that the proposed ECC circuit achieves smaller area and higher reliability than the full memristor-based ECC circuits and achieves much smaller area while preserving the reliability compared with the full CMOS-based ECC circuits.

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Acknowledgements

This work was partially supported by JSPS KAKENHI Grant No. 18K18025.

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Authors and Affiliations

  1. Nara Institute of Science and Technology (NAIST), 8916-5 Takayama-cho, Ikoma, Nara, 630-0192, Japan

    Mamoru Ishizaka, Michihiro Shintani & Michiko Inoue

Authors
  1. Mamoru Ishizaka
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  2. Michihiro Shintani
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  3. Michiko Inoue
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Correspondence to Michihiro Shintani.

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Responsible Editor: K. Chakrabarty

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Ishizaka, M., Shintani, M. & Inoue, M. Area-Efficient and Reliable Error Correcting Code Circuit Based on Hybrid CMOS/Memristor Circuit. J Electron Test 36, 537–546 (2020). https://doi.org/10.1007/s10836-020-05892-3

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  • DOI: https://doi.org/10.1007/s10836-020-05892-3

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