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Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack

Abstract

We propose an architecture for a Field Programmable Gate Array (FPGA) based tester for a 3D stacked integrated circuit (IC). Due to the very short distances between dies in a stack that can make SerDes connections very efficient and the high density of through silicon vias (TSVs) that may be available, it is possible to connect the FPGA to the die under test through a very high bandwidth connection that can feed multiple short scan chains. We propose and evaluate two designs that exploit the underlying structure of the FPGA, allowing it to be used to efficiently store and apply predefined test patterns, reducing the FPGA resources required and the switching activity in the circuit under test when compared to a more traditional on-chip decompressor implemented to feed short scan chains. For the largest circuit we studied, the switching activity was reduced about 80% and the test time by 90%.

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Notes

  1. In order to achieve high test coverage, the number of top off patterns could be quite significant. Exploring how to decrease the top-off patterns is left for future work.

  2. By uncompressed, we mean the patterns are generated without an on-chip decompressor, but still after the dynamic pattern compression from the ATPG tool.

  3. Note that the length of the scan chain can have a bearing on the number of patterns produced from an on-chip decompressor [4] with larger chains leading to fewer patterns.

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Correspondence to Yi Sun.

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This work was supported in part by NSF grant CCF-1814928 and CCF-1812777.

Responsible Editor: T. Xia

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Sun, Y., Zhang, F., Jiang, H. et al. Repurposing FPGAs for Tester Design to Enhance Field-Testing in a 3D Stack. J Electron Test 35, 887–900 (2019). https://doi.org/10.1007/s10836-019-05845-5

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Keywords

  • Design for testabiliy (DFT)
  • Low power test
  • On-chip decompressor