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Classical Cryptanalysis Attacks on Logic Locking Techniques

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Abstract

Logic locking is a protection technique for outsourced integrated circuit (IC) designs that thwarts IC piracy and IC counterfeiting by untrusted foundries. In this technique, the IC design house locks the correct functionality of the circuit using a key that is known only to the trusted entities in the design house. As the correct key values are provided by the design house after production, a malicious adversary in the foundry house will not be able to unlock overproduced or counterfeit ICs. In this paper, we mount linear approximation attacks and differential attacks on random logic locking (RLL), fault-analysis based logic locking (FLL), and strong logic locking (SLL) techniques. We present a formal approach to mount the linear approximation attack on multiple circuit partitions and thereafter combining the approximations to form the attack on a locked logic cone of the circuit. We present our results on ISCAS’85 benchmark circuits. In linear approximation attack, the combinatorial blocks are partitioned and expressed as linear expressions to derive a relation between the primary inputs and the primary outputs of the circuit. The attack aims to determine the linear approximation that has the highest probability of occurrence for the correct key input. In differential attacks, we could recover the embedded secret key in device with attack effort lesser than exhaustive search attack.

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Notes

  1. An initial version of this paper has been published with title, “Linear Approximation and Differential Attacks on Logic Locking Techniques”, in 32nd International Conference on VLSI Design, VLSID 2019, Delhi, India, January 5-9, 2019. In this paper, we present a formal method to determine the probability of occurrences of the linear approximations across multiple partitions that will guide an cryptanalyst to choose suitable approximations to recover the secret key.

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Authors and Affiliations

  1. Discipline of Computer Science and Engineering, Indian Institute of Technology Indore, Indore, India

    Bodhisatwa Mazumdar, Ghanshyam Bairwa, Souvik Mandal & Tatavarthy Venkat Nikhil

  2. Department of Computer Science and Engineering, SGSITS Indore, Indore, India

    Soma Saha

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  1. Bodhisatwa Mazumdar
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  2. Soma Saha
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  3. Ghanshyam Bairwa
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  5. Tatavarthy Venkat Nikhil
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Correspondence to Bodhisatwa Mazumdar.

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Mazumdar, B., Saha, S., Bairwa, G. et al. Classical Cryptanalysis Attacks on Logic Locking Techniques. J Electron Test 35, 641–654 (2019). https://doi.org/10.1007/s10836-019-05838-4

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  • DOI: https://doi.org/10.1007/s10836-019-05838-4

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