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Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness

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Abstract

The physical unclonable functions (PUFs) are used to provide software as well as hardware security for the cyber-physical systems. They have been used for performing significant cryptography tasks such as generating keys, device authentication, securing against IP piracy, and to produce the root of trust as well. However, they lack in reliability metric. We present a novel approach for improving the reliability as well as the uniqueness of the field programmable gated arrays (FPGAs) based ring oscillator PUF and derive a random number, consuming very small area (< 1%) concerning look-up tables (LUTs). We use frequency profiling method for distributing frequency variations in ring oscillators (RO), spatially placed all across the FPGA floor. We are able to spot suitable locations for RO mapping, which leads to enhanced ROPUF reliability. We have evaluated the proposed methodology on Xilinx -7 series FPGAs and tested the robustness against environmental variations, e.g. temperature and supply voltage variations, simultaneously. The proposed approach achieves significant improvement (i) in uniqueness value upto 49.90%, within 0.1% of the theoretical value (ii) in the reliability value upto 99.70%, which signifies that less than 1 bit flipping has been observed on average, and (iii) in randomness, signified by passing NIST test suite. The response generated through the ROPUF passes all the applicable relevant tests of NIST uniformity statistical test suite.

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  • 19 December 2019

    The original article unfortunately contained a mistake. Corrections provided in a list form were not carried out.

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Acknowledgements

We also gratefully acknowledge SMDP-C2SD project (ODRC No. 1000110086) project funded by Ministry of Electronics & IT, Government of India for technical support. We are thankful to Mr Bharat Kasyap, MNIT, Jaipur to provide support for experimental setup design.

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Authors and Affiliations

  1. Malaviya National Institute of Technology, JLN Marg, Jaipur, Rajasthan, India

    Arjun Singh Chauhan & Vineet Sahula

  2. Cognitive Computing GroupCEERI Pilani, Pilani, Rajasthan, India

    Atanendu Sekhar Mandal

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  1. Arjun Singh Chauhan
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  2. Vineet Sahula
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  3. Atanendu Sekhar Mandal
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Correspondence to Vineet Sahula.

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The original version of this article was revised: A number of corrections from the author were not carried out.

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Chauhan, A.S., Sahula, V. & Mandal, A.S. Novel Randomized Placement for FPGA Based Robust ROPUF with Improved Uniqueness. J Electron Test 35, 581–601 (2019). https://doi.org/10.1007/s10836-019-05829-5

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