A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip


Networks-on-chip (NoC) provide the communication infrastructure for high-speed and large-scale computation that integrates several IP-cores on a single die. Faults on network channels severely degrade system performance and throughput. This paper presents a distributed and online mechanism for detecting and locating stuck-at faults (SAFs) in NoC channels. We also study the effects of such faults on various network performance metrics. The inherent parallelism present in the architecture is utilized to design a scheduling scheme that reduces the overall test time and overhead significantly. The proposed test solution scales well with network size, channel width, and network topology. Hardware synthesis based on FPGA shows that it needs small area overhead and low test time compared to prior approaches. Furthermore, it improves packet latency and reduces energy consumption.

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    In a test iteration either the nodes on an odd/even diagonal level execute the 1-step algorithm only. This node selection is comparable to a coin tossing that results in either head/tail mark where appearance of head results in selection of nodes at an odd diagonal level. On the contrary, nodes on an even diagonal level may be selected on the appearance of tail. The diagonal model (D-Model) and Toss-Model are interchangeable used in the rest of the paper.

  2. 2.

    The labels R1, R2 in this figure and later part of the paper represent TR=I, TR=II, respectively.


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Bhowmik, B., Biswas, S., Deka, J.K. et al. A Low-Cost Test Solution for Reliable Communication in Networks-on-Chip. J Electron Test 35, 215–243 (2019). https://doi.org/10.1007/s10836-019-05792-1

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  • Channel-faults
  • Networks-on-chip (NoC)
  • System reliability
  • Performance