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Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design

Journal of Electronic Testing volume 34, pages 53–65 (2018)Cite this article

Abstract

Automatic test pattern generation (ATPG) is the next step after synthesis in the process of chip manufacturing. The ATPG may not be successful in generating tests for all multiple stuck-at faults since the number of fault combinations is large. Hence a need arises for highly testable designs which have 100% fault efficiency under the multiple stuck-at fault(MSAF) model. In this paper we investigate the testability of ROBDD based 2×1 mux implemented combinational circuit design. We show that the ROBDD based 2×1 mux implemented circuit is fully testable under multiple stuck-at fault model. Principles of pseudoexhaustive testing and multiple stuck-at fault testing of two level AND-OR gates are applied to one sub-circuit(2×1 mux). We show that the composite test vector set derived for all 2×1 muxes is capable of detecting multiple stuck-at faults of the circuit as a whole. Algorithms to derive test set for multiple stuck-at faults are demonstrated. The multiple stuck-at fault test set is larger than the single stuck-at fault test set. We show that the multiple stuck-at fault test set can be derived from the Disjoint Sum of Product expression which allows test pattern generation at design time, eliminating the need of an ATPG after the synthesis stage.

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Authors and Affiliations

  1. CADSL, Department of Electrical Engineering, Indian Institute of Technology Bombay, Main Gate Road, Powai, Mumbai, Maharashtra, 400076, India

    Toral Shah

  2. Department of Applied Mathematics and Cybernatics, Tomsk State University, Lenin Ave, 36, Tomsk, Tomskaya oblast’, 634050, Russia

    Anzhela Matrosova

  3. VLSI Design and Education Center, University of Tokyo, 7 Chome-3-1 Hongo, Bunkyo, Tokyo, 113-8654, Japan

    Masahiro Fujita

  4. Virendra Singh, CADSL, Department of Electrical Engineering, Indian Institute of Technology Bombay, Main Gate Road, Powai, Mumbai, Maharashtra, 400076, India

    Virendra Singh

Authors
  1. Toral Shah
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  2. Anzhela Matrosova
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  3. Masahiro Fujita
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  4. Virendra Singh
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Correspondence to Toral Shah.

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Responsible Editor: L. M. Bolzani Pöhls

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Shah, T., Matrosova, A., Fujita, M. et al. Multiple Stuck-at Fault Testability Analysis of ROBDD Based Combinational Circuit Design. J Electron Test 34, 53–65 (2018). https://doi.org/10.1007/s10836-018-5703-3

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  • DOI: https://doi.org/10.1007/s10836-018-5703-3

Keywords

  • ROBDD
  • Combinational logic
  • Multiple stuck-at faults
  • Disjoint sum of products
  • Test generation