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A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems

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Abstract

Hardware devices of recent technology nodes are intrinsically more susceptible to faults than previous devices. This demands further improvements of error detection methods. However, any attempt to cover all errors for all theoretically possible scenarios that a system might be used in can easily lead to excessive costs. Instead, an application-dependent approach should be taken, i.e., strategies for test and error resilience must target only those errors that can actually have an effect in the situations in which the hardware is being used. In this paper, we propose a method to inject faults into hardware (HW) and to formally analyze their effects on the software (SW) behavior. We describe how this analysis can be implemented based on a recently proposed HW-dependent software model called program netlist (PN). We show how program netlists can be extended to formally model the behavior of a program in the event of one or more hardware faults. Then, it is demonstrated how the results of the PN-based analysis can be exploited by a standard ATPG tool to determine hardware faults at the gate level that are “application-redundant”. Our experimental results show the feasibility of the proposed approach.

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Authors and Affiliations

  1. Department of Electrical and Computer Engineering, University of Kaiserslautern, Kaiserslautern, Germany

    Christian Bartsch, Carlos Villarraga, Dominik Stoffel & Wolfgang Kunz

Authors
  1. Christian Bartsch
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  2. Carlos Villarraga
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  3. Dominik Stoffel
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  4. Wolfgang Kunz
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Correspondence to Carlos Villarraga.

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Responsible Editor: L. M. Bolzani Pöhls

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Bartsch, C., Villarraga, C., Stoffel, D. et al. A HW/SW Cross-Layer Approach for Determining Application-Redundant Hardware Faults in Embedded Systems. J Electron Test 33, 77–92 (2017). https://doi.org/10.1007/s10836-017-5643-3

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  • DOI: https://doi.org/10.1007/s10836-017-5643-3

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