FinFET technology has become the most promising alternative to continue CMOS scaling due to its improved short channel effects. Design flexibility reduces on FinFET based circuits such as SRAM cells due to the effective channel width is determined by an integer number of fins. In this work, the impact of fin height size of FinFET transistors on the simultaneous behavior of soft error sensitivity and SRAM cell static noise margin is investigated. 3-D TCAD Sentarus environment is used to quantify the amount of collected and critical charges of an SRAM cell due to a heavy ion strike while Mix-Mode Hspice-TCAD simulation is used for stability analysis. Even more, the influence of process variations on sensitivity to soft errors and cell stability is considered. A 10 nm-SOI Tri-Gate FinFET technology is used. Results show that increasing the fin height of FinFET transistors considerably increases SRAM cell sensitivity to soft errors but improves its stability. This suggests that the optimum fin height value of FinFET transistors of an SRAM cell depends on the best tradeoff between soft error robustness and stability.
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Hector Villacorta would like to thank CONACYT for the scholarship support under the postgraduate program with contract No. 212460. Jaume Segura acknowledges support from the Spanish Ministry of Economics and Competitivity and the Regional European Development funds (FEDER) from EU under project TEC2011-25017.
Responsible Editor: L. M. Bolzani Pöhls
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Villacorta, H., Segura, J. & Champac, V. Impact of Fin-Height on SRAM Soft Error Sensitivity and Cell Stability. J Electron Test 32, 307–314 (2016). https://doi.org/10.1007/s10836-016-5591-3
- Soft errors
- Static noise margin
- Process variations