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A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding

Abstract

A power efficient System-on-a-Chip test data compression method using alternating statistical run-length coding is proposed. To effectively reduce test power dissipation, the test set is firstly preprocessed by 2D reordering scheme. To further improve the compression ratio, 4 m partitioning of the runs and a smart filling of the don’t care bits provide the nice results, and alternating statistical run-length coding scheme is developed to encode the preprocessed test set. In addition, a simple decoder is obtained which consumed a little area overhead. The benchmark circuits verify the proposed power efficient coding method well. Experimental results show it obtains a high compression ratio, low scan-in test power dissipation and little extra area overhead during System-on-a-Chip scan testing.

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Acknowledgments

This research work was supported by the National Natural Science Foundation of China (61001049, 61372149 and 61370189) and Scholarship sponsored by China Scholarship Council [2013] 3018.

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Correspondence to Haiying Yuan.

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Responsible Editor: N. A. Touba

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Yuan, H., Guo, K., Sun, X. et al. A Power Efficient Test Data Compression Method for SoC using Alternating Statistical Run-Length Coding. J Electron Test 32, 59–68 (2016). https://doi.org/10.1007/s10836-016-5562-8

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Keywords

  • Don’t care bit filling
  • Test data compression
  • Test power dissipation
  • Area overhead
  • Alternating statistical run-length code