This paper proposes a small chip area stochastic calibration for TDC linearity and input range, and analyzes it with FPGA. The proposed calibration estimates the absolute values of the delay of the buffers and the range of measurement statistically. The hardware implementation of the proposed calibration requires single counter to construct the histogram, so that the extra area for the proposed calibration is smaller. Because the implementation is fully digital, it is easily implemented on digital LSIs such as FPGA, micro-processor, and SoC. Experiments with Xilinx Virtex-5 LX FPGA ML501 reveal that both the periods of the external clock and the ring oscillator are preferred as short as possible under more than twice of the range of measurement of TDC when the oscillation period of the ring oscillator is wider than that of the external clock for fast convergence. The required time for the proposed calibration is 0.08 ms, and the required hardware resources LUTs and FFs for the implementation on FPGA are 24.1% and 22.2% of the conventional implementation, respectively.
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This work is supported by the Semiconductor Technology Academic Research Center (STARC). The authors acknowledge Prof. Nobukazu Takai who gave us the variable suggestions.
Responsible Editor: J.-L. Huang
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Katoh, K., Kobayashi, Y., Chujo, T. et al. A Small Chip Area Stochastic Calibration for TDC Using Ring Oscillator. J Electron Test 30, 653–663 (2014). https://doi.org/10.1007/s10836-014-5486-0
- Stochastic calibration
- Self compensation
- Self Test