Multi-bit Sigma-Delta TDC Architecture with Improved Linearity

Abstract

This paper describes the architecture and principles of operation of sigma-delta ( ΣΔ) time-to-digital converters (TDC) for high-speed I/O interface circuit test applications. In particular, we describe multi-bit ΣΔ TDC architectures; they offer good accuracy with short testing time. However, mismatches among delay cells in delay lines degrade their linearity. Here we propose two methods to improve the overall TDC linearity: a data-weighted-average (DWA) algorithm, and a self-calibration method that measures delay values using a ring oscillator circuit. Our Matlab simulation results demonstrate the effectiveness of these approaches.

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Acknowledgment

We acknowledge comments from K. Sato, S. Kawauchi, F. Abe, K. Sakuma and K. Wilkinson.

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Correspondence to Haruo Kobayashi.

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Responsible Editor: M. Margala

Appendix: Improved Delay Measurement Circuit

Appendix: Improved Delay Measurement Circuit

This appendix shows an improved delay-value self-measurement circuit in Fig. 18, and we can use it when the rise delay time τ r and the fall delay time τ f of the delay cell are quite different.

The oscillation frequency f o s c of the basic ring-oscillator configuration in Fig. 10 is a function of the buffer delay τ. Note that τ is the average of τ r and τ f (i.e., τ = (τ r + τ f ) / 2), where τ r is the delay when the buffer output rises from low to high level, and τ f is the one when it falls from high to low level. However, we need the value of τ r and we cannot measure it accurately with the ring oscillator in Fig. 10 when τ r and τ f are not equal.

The oscillation frequency of the improved circuit in Fig. 18a is only a function of τ r but is not a function of τ f . Figure 18b shows the timing chart of its signals for τ r < τ f . We have checked its operation with Spectre simulation.

Fig. 18
figure18

a Oscillator circuit to measure the rise delay of the buffer. b Timing chart

By replacing one of the five buffers from node “a” to node “b” in Fig. 18a with the buffer in Fig. 5 whose rise delay τ r(m e a s u r e) should be measured, we can obtain the accurate value of τ r(m e a s u r e) by measuring the oscillation frequency.

Remark 3

  1. (i)

    We need to design the buffer delay in Fig. 5 intentionally to satisfy τ r < τ f to use the circuit in Fig. 18 for self-calibration.

  2. (ii)

    The circuit works even if τ r > τ f with replacing AND gate with OR gate, and OR gate with AND gate.

  3. (iii)

    A similar circuit to the one in Fig. 18 is shown in [7].

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Uemori, S., Ishii, M., Kobayashi, H. et al. Multi-bit Sigma-Delta TDC Architecture with Improved Linearity. J Electron Test 29, 879–892 (2013). https://doi.org/10.1007/s10836-013-5408-6

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Keywords

  • Time-to-digital converter
  • Time measurement
  • Sigma-delta modulation
  • Multi-bit
  • Calibration
  • High-speed I/O interface circuit testing