Advertisement

Journal of Electronic Testing

, Volume 28, Issue 4, pp 511–521 | Cite as

Identifying Untestable Faults in Sequential Circuits Using Test Path Constraints

  • Taavi Viilukas
  • Anton Karputkin
  • Jaan RaikEmail author
  • Maksim Jenihhin
  • Raimund Ubar
  • Hideo Fujiwara
Article

Abstract

The paper proposes a hierarchical untestable stuck-at fault identification method for non-scan synchronous sequential circuits. The method is based on deriving, minimizing and solving test path constraints for modules embedded into Register-Transfer Level (RTL) designs. First, an RTL test pattern generator is applied in order to extract the set of all possible test path constraints for a module under test. Then, the constraints are minimized using an SMT solver Z3 and a logic minimization tool ESPRESSO. Finally, a constraint-driven deterministic test pattern generator is run providing hierarchical test generation and untestability proof in sequential circuits. We show by experiments that the method is capable of quickly proving a large number of untestable faults obtaining higher fault efficiency than achievable by a state-of-the-art commercial ATPG. As a side effect, our study shows that traditional bottom-up test generation based on symbolic test environment generation at RTL is too optimistic due to the fact that propagation constraints are ignored.

Keywords

Automated test pattern generation Untestable faults Register-transfer level 

Notes

Acknowledgments

The work has been supported by European Commission Framework Program 7 project FP7-ICT-2009-4-248613 DIAMOND, by Research Centre CEBE funded by European Union through the European Structural Funds and by Estonian Science Foundation grants 9429 and 8478.

References

  1. 1.
    Agrawal VD, Chakradhar ST (1995) Combinational ATPG theorems for identifying untestable faults in sequential circuits. IEEE Trans Comput Aided Des 14(9):1155–1160CrossRefGoogle Scholar
  2. 2.
    Brayton RK, Hachtel GD, McMullen CT, Sangiovanni-Vincentelli AL (1984) Logic Minimization Algorithms for VLSI Synthesis. Kluwer Academic Publishers, BostonGoogle Scholar
  3. 3.
    Chayakul V, Gajski DD, Ramachandran L (1993) High-Level Transformations for Minimizing Syntactic Variances, DAC (Proceedings of the Design Automation Conference), Dallas, Texas, USA, p 413–418Google Scholar
  4. 4.
    De Moura L, Bjørner N (2008) Z3: An Efficient SMT Solver. TACAS (International Conference on Tools and Algorithms for the Construction and Analysis of Systems (TACAS)), Budapest, Hungary, p 337–340Google Scholar
  5. 5.
    Dillig I, Dillig T, Aiken A (2010) Small Formulas for Large Programs, Proc. of the 17th intl. conf. on Static Analysis, Springer-Verlag, Berlin, Heidelberg, p 236–252Google Scholar
  6. 6.
    Fujiwara H, Ooi CY, Shimizu Y (2008) Enhancement of Test Environment Generation for Assignment Decision Diagrams, 9th IEEE Workshop on RTL and High Level Testing, Nov. IEEE, Sapporo, Japan, 45–50Google Scholar
  7. 7.
    Ghosh I, Fujita M (2000) Automatic test pattern generation for functional RTL circuits using assignment decision diagrams, Proc. DAC (Proceedings of the Design Automation Conference), Los Angeles, California, USA, p 43–48Google Scholar
  8. 8.
  9. 9.
  10. 10.
    Iyer MA, Long DE, Abramovici M (1996) Identifying sequential redundancies without search. In: Proc. 33rd Annu. Conf. DAC, LasVegas, pp 457–462Google Scholar
  11. 11.
    Jervan G et al (2002) High-Level and Hierarchical Test Sequence Generation. IEEE HLDVT, Cannes, 169–174Google Scholar
  12. 12.
    Lee J, Patel JH (1994 Oct) Architectural level test generation for microprocessors, IEEE Trans. CAD (IEEE Transactions on CAD of Integrated Circuits and Systems), Piscataway, New Jersey, USA, p 1288–1300Google Scholar
  13. 13.
    Liang H-C, Lee CL, Chen EJ (1995) Identifying untestable faults in sequential circuits. IEEE Des Test Comput 12(3):14–23CrossRefGoogle Scholar
  14. 14.
    Long DE, Iyer MA, Abramovici M (2000) FILL and FUNI: Algorithms to identify illegal states and sequentially untestable faults. ACM Trans Des Autom Electron Syst 5(3):631–657CrossRefGoogle Scholar
  15. 15.
    Murray BT, Hayes JP (1988) Hierarchical test generation using precomputed tests for modules, Proc. ITC (Proceedings of the International Test Conference), Washington, D.C., USA, p 221–229Google Scholar
  16. 16.
    Peng Q, Abramovici M, Savir J (2000) MUST: multiple stem analysis for identifying sequential untestable faults. In: Proc. Int. Test Conf. IEEE, Atlantic City, NJ, USA, p 839–846Google Scholar
  17. 17.
    Raik J, Fujiwara H, Ubar R, Krivenko A (2008) Untestable fault identification in sequential circuits using model-checking. ATS (Proceedings of the Asian Test Symposium), Sapporo, Japan, p 667–672Google Scholar
  18. 18.
    Raik J, Rannaste A, Jenihhin M, Viilukas T, Ubar R, Fujiwara H (2011) Constraint-Based Hierarchical Untestability Identification for Synchronous Sequential Circuits, Proc. of the European Test Symposium, IEEE Computer Society, Trondheim, Norway, p 147–152Google Scholar
  19. 19.
    Raik J, Ubar R (1999) Sequential Circuit Test Generation Using Decision Diagram Models, Proceedings of the DATE Conference, IEEE Computer Society, Munich, Germany, p 736–740Google Scholar
  20. 20.
    The ECLiPSe Constraint Programming System http://eclipseclp.org/
  21. 21.
    Vedula V, Abraham J (2002) FACTOR: A Hierarchical Methodology for Functional Test Generation and Testability Analysis, DATE Conf., IEEE Computer Society, Paris, France, p 730–734Google Scholar
  22. 22.
    Viilukas T, Raik J, Jenihhin M, Ubar R, Krivenko A (2010) Constraint-based test pattern generation at the register-transfer level, 13th IEEE DDECS Symposium, IEEE Computer Society, Vienna, Austria, p 352–357Google Scholar
  23. 23.
    Zhang L, Ghosh I, Hsiao M (2003) Efficient Sequential ATPG for Functional RTL Circuits, Int. Test Conf., IEEE, Charlotte, NC, USA, p 290–298Google Scholar

Copyright information

© Springer Science+Business Media, LLC 2012

Authors and Affiliations

  • Taavi Viilukas
    • 1
  • Anton Karputkin
    • 1
  • Jaan Raik
    • 1
    Email author
  • Maksim Jenihhin
    • 1
  • Raimund Ubar
    • 1
  • Hideo Fujiwara
    • 2
  1. 1.Department of Computer EngineeringTallinn University of TechnologyTallinnEstonia
  2. 2.Faculty of InformaticsOsaka Gakuin UniversitySuitaJapan

Personalised recommendations