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Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns

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Abstract

This paper presents a new reseeding technique that reduces the storage required for the seeds as well as the test application time by alternating between ATPG and reseeding to optimize the seed selection. The technique avoids loading a new seed into the PRPG whenever the PRPG can be placed in a state that generates test patterns without explicitly loading a seed. The ATPG process is tuned to target only undetected faults as the PRPG goes through its natural sequence which is maximally used to generate useful test patterns. The test application procedure is slightly modified to enable higher flexibility and more reduction in tester storage and test time. The results of applying the technique show up to 90% reduction in tester storage and 80% reduction in test time compared to classic reseeding. They also show 70% improvement in defect coverage when the technique is emulated on test chips with real defects.

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Acknowledgments

This work was supported by King Fahd University of Petroleum and Minerals and by LSI Logic under contract No. 16517.

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Authors and Affiliations

  1. Computer Engineering Department, KFUPM, Dhahran, Saudi Arabia

    Ahmad A. Al-Yamani

  2. Stanford Center for Reliable Computing, Stanford University, Stanford, CA, 94305, USA

    Edward J. McCluskey

Authors
  1. Ahmad A. Al-Yamani
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  2. Edward J. McCluskey
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Correspondence to Ahmad A. Al-Yamani.

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Responsible Editor: K. Chakrabarty

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Al-Yamani, A.A., McCluskey, E.J. Test Set Compression Through Alternation Between Deterministic and Pseudorandom Test Patterns. J Electron Test 26, 513–521 (2010). https://doi.org/10.1007/s10836-010-5172-9

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  • DOI: https://doi.org/10.1007/s10836-010-5172-9

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