Abstract
Gate-all-around field-effect transistors deliver the best inversion layer control among the family of multi-gate transistors and are proving to be the promising architecture for logic nodes beyond 10 nm. Sub-10 nm devices typically have effective oxide thickness below 1 nm and a higher mobility channel for faster switching. However, the thinner oxide barrier and lower effective mass of the channel material both aid gate leakage, which is one of the metrics for the scaling limit. This paper presents a 2D finite element method (FEM)-based model that accurately calculates gate leakage current from the quasi-bound states (QBS) that exist in the inversion layer of the nanowire. The lifetime of QBS is calculated considering the scattered cylindrical waves in the open system by solving Schrödinger’s equation using the FEM. The impact of channel and oxide material, channel diameter, strain in the nanowire, and oxide thickness on gate leakage current density is investigated.
Similar content being viewed by others
Availability of data and material
Data is taken from already published work and has public access.
Code availability
Custom codes are developed based on open-source software packages Dune-Numerics and PETSc-SLEPc.
References
Kuhn, K.J.: Considerations for ultimate CMOS scaling. IEEE Trans. Electron Devices 59(7), 1813–1828 (2012)
Park, J.T., Colinge, J.P.: Multiple-gate SOI MOSFETS: device design guidelines. IEEE Trans. Electron Devices 49(12), 2222–2229 (2002)
Mehrotra, S.R., Kim, S., Kubis, T., Povolotskyi, M., Lundstrom, M.S., Klimeck, G.: Engineering nanowire n-MOSFETS at \(l_{g} <8nm\). IEEE Trans. Electron Devices 60(7), 2171–2177 (2013)
Appenzeller, J., Knoch, J., Bjork, M.T., Riel, H., Schmid, H., Riess, W.: Toward nanowire electronics. IEEE Trans. Electron Devices 55(11), 2827–2845 (2008)
Li, M., Yeo, K.H., Suk, S.D., Yeoh, Y.Y., Kim, D.-W., Chung, T.Y., Oh, K.S., Lee, W.-S.: Sub-10 nm gate-all-around CMOS nanowire transistors on bulk SI substrate. In: VLSI Technology: Symposium on. IEEE, 2009, pp 94–95 (2009)
Yeo, K.H., Suk, S.D., Li, M., Yeoh, Y.-Y., Cho, K.H., Hong, K.-H., Yun, S., Lee, M.S., Cho, N., Lee, K., Gate-all-around (GAA) twin silicon nanowire MOSFET (TSNWFET) with 15 nm length gate and 4 nm radius nanowires. In: Electron Devices Meeting, et al.: IEDM’06, pp. 1–4. International. IEEE (2006)
Jiang, Y., Liow, T.Y., Singh, N., Tan, L., Lo, G.Q., Chan, D.S.H., Kwong, D.L.: Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts.’ In: IEEE, pp. 34–35 (2008)
Singh, N., Lim, F., Fang, W., Rustagi, S., Bera, L., Agarwal, A., Tung, C., Hoe, K., Omampuliyur, S., Tripathi, D.: Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance. In: Electron Devices Meeting, et al.: IEDM’06. International, pp. 1–4. IEEE (2006)
Auth, C., Plummer, J.: Scaling theory for cylindrical, fully-depleted, surrounding-gate MOSFETs. IEEE Electron Device Lett. 18(2), 74–76 (1997)
Lu, W., Xie, P., Lieber, C.M.: Nanowire transistor performance limits and applications. IEEE Trans. Electron Devices 55(11), 2859–2876 (2008)
Fischetti, M.V., Fu, B., Vandenberghe, W.G.: Theoretical study of the gate leakage current in sub-10-nm field-effect transistors. IEEE Trans. Electron Devices 60(11), 3862–3869 (2013)
Chowdhury, N., Iannaccone, G., Fiori, G., Antoniadis, D.A., Palacios, T.: Gan nanowire n-MOSFET with 5 nm channel length for applications in digital electronics. IEEE Electron Device Lett. 38(7), 859–862 (2017)
Salmani-Jelodar, M., Mehrotra, S.R., Ilatikhameneh, H., Klimeck, G.: Design guidelines for sub-12 nm nanowire MOSFETs. IEEE Trans. Nanotechnol. 14(2), 210–213 (2015)
Hashemi, P., Gomez, L., Canonico, M., Hoyt, J.L.: Electron transport in gate-all-around uniaxial tensile strained-SI nanowire n-MOSFETs. In: Electron Devices Meeting: IEDM 2008. IEEE International, pp. 1–4. IEEE (2008)
Spinelli, A.S., Compagnoni, C., Monzio, M., Maconi, A., Amoroso, S.M., Lacaita, A.L.: Quantum-mechanical charge distribution in cylindrical gate-all-around MOS devices. IEEE Trans. Electron Devices 59(7), 1837–1843 (2012)
Luisier, M., Schenk, A., Fichtner, W.: ‘Three-dimensional modeling of gate leakage in SI nanowire transistors. IEEE 733–736 (2007)
Cao, W., Shen, C., Cheng, S.Q., Huang, D.M., Yu, H.Y., Singh, N., Lo, G.Q., Kwong, D.L., Li, M.-F.: Gate tunneling in nanowire MOSFETs. IEEE Electron Device Lett. 32(4), 461–463 (2011)
Tiwari, S., Rana, F., Hanafi, H., Hartstein, A., Crabbé, E.F., Chan, K.: A silicon nanocrystals based memory. Appl. Phys. Lett. 68(10), 1377–1379 (1996)
Geuzaine, C., Remacle, J.-F.: Gmsh: a 3-d finite element mesh generator with built-in pre-and post-processing facilities. Int. J. Numer. Methods Eng 79(11), 1309–1331 (2009)
Mahajan, A., Gawhane, D., Patrikar, R.: Finite element modeling of Fowler–Nordheim program-erase process in high-\(k\) interpoly dielectric flash memories. IEEE Trans. Electron Devices 63(12), 4729–4736 (2016)
Solanki, R., Mahajan, A., Patrikar, R.: Finite-element modeling of retention in nanocrystal flash memories with high-\(k\) interpoly dielectric stack. IEEE Trans. Electron Devices 64(12), 4897–4903 (2017)
Perelomov, A.M., Zel’dovich, Y.B.: Quasi-stationary states. In: Quantum Mechanics, Selected Topics, pp. 255–304. World Scientific (1998)
Arfken, G.B., Weber, H.J.: Mathematical methods for physicists, pp. 671–675 (1999)
Bastian, P., Blatt, M., Dedner, A., Engwer, C., Klöfkorn, R., Ohlberger, M., Sander, O.: A generic grid interface for parallel and adaptive scientific computing part I: abstract framework. Computing 82(2–3), 103–119 (2008)
Hernandez, V., Roman, J.E., Vidal, V.: Slepc, a scalable and flexible toolkit for the solution of eigenvalue problems. ACM Trans Math. Softw. 31(3), 351–362 (2005)
dos Santos, C.L., Piquini, P.: Diameter dependence of mechanical, electronic, and structural properties of INAS and INP nanowires: a first-principles study. Phys. Rev. B 81(7), 2010 (2010)
Vilela, T., Alves, H.W.L.: Atomic and electronic properties of GAN nanowires. Phys. Procedia 28, 17–21 (2012)
Chang, Y., Huang, M., Chang, Y., Lee, Y., Chiu, H., Kwo, J., Hong, M.: Atomic-layer-deposited al\(_2\)o\(_3\) and hfo\(_2\) on GAN: a comparative study on interfaces and electrical characteristics. Microelectron. Eng. 88(7), 1207–1210 (2011)
Acknowledgements
The authors would like to acknowledge Mr. Yogesh Agarwal, Ms. Rosalina Sahoo, and Ms. Meena Tulasi for the helpful discussion.
Funding
This work is not supported by any funding agency.
Author information
Authors and Affiliations
Corresponding author
Ethics declarations
Conflict of interest
The authors have declared no competing interest.
Additional information
Publisher's Note
Springer Nature remains neutral with regard to jurisdictional claims in published maps and institutional affiliations.
Rights and permissions
About this article
Cite this article
Solanki, R., Minase, S., Mahajan, A. et al. Modeling of gate leakage in cylindrical gate-all-around transistors. J Comput Electron 20, 1694–1701 (2021). https://doi.org/10.1007/s10825-021-01766-9
Received:
Accepted:
Published:
Issue Date:
DOI: https://doi.org/10.1007/s10825-021-01766-9