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Modeling of gate leakage in cylindrical gate-all-around transistors

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Abstract

Gate-all-around field-effect transistors deliver the best inversion layer control among the family of multi-gate transistors and are proving to be the promising architecture for logic nodes beyond 10 nm. Sub-10 nm devices typically have effective oxide thickness below 1 nm and a higher mobility channel for faster switching. However, the thinner oxide barrier and lower effective mass of the channel material both aid gate leakage, which is one of the metrics for the scaling limit. This paper presents a 2D finite element method (FEM)-based model that accurately calculates gate leakage current from the quasi-bound states (QBS) that exist in the inversion layer of the nanowire. The lifetime of QBS is calculated considering the scattered cylindrical waves in the open system by solving Schrödinger’s equation using the FEM. The impact of channel and oxide material, channel diameter, strain in the nanowire, and oxide thickness on gate leakage current density is investigated.

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Data is taken from already published work and has public access.

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Custom codes are developed based on open-source software packages Dune-Numerics and PETSc-SLEPc.

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Acknowledgements

The authors would like to acknowledge Mr. Yogesh Agarwal, Ms. Rosalina Sahoo, and Ms. Meena Tulasi for the helpful discussion.

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Correspondence to Ashutosh Mahajan.

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Solanki, R., Minase, S., Mahajan, A. et al. Modeling of gate leakage in cylindrical gate-all-around transistors. J Comput Electron 20, 1694–1701 (2021). https://doi.org/10.1007/s10825-021-01766-9

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  • DOI: https://doi.org/10.1007/s10825-021-01766-9

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