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The design, analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approach

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Abstract

The quantum-dot cellular automata (QCA) is considered to be one of the ground-breaking nanotechnologies developed over the last two decades. A layered T (LT) logic cell library is constructed herein, and the methodology is extended to generic adder and subtractor module designs. The two proposed algorithms lead to more efficient QCA layout designs for an n-bit ripple carry adder (RCA) and subtractor based on an effective clock zone assignment approach. The suggested one-, four-, and eight-bit RCAs and subtractors surpass most of their existing counterparts by offering lower effective area and cell complexity. A comparative analysis is presented regarding the complexity, irreversible power dissipation, and Costα of the proposed n-bit layouts from a cost estimation purview.

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Acknowledgements

The authors would like to thank Prof. Debdatta Banerjee for her literary contribution to this work.

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Authors and Affiliations

  1. Department of Electronics and Communication Engineering, University of Engineering and Management, Jaipur, Rajasthan, India

    Chiradeep Mukherjee

  2. Department of Electronics and Communication Engineering, Narula Institute of Technology, Kolkata, West Bengal, India

    Saradindu Panda & Asish Kumar Mukhopadhyay

  3. Department of Electronics and Communication Engineering, National Institute of Technology, Durgapur, West Bengal, India

    Chiradeep Mukherjee & Bansibadan Maji

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  1. Chiradeep Mukherjee
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Mukherjee, C., Panda, S., Mukhopadhyay, A.K. et al. The design, analysis, and cost estimation of a generic adder and subtractor using the layered T (LT) logic reduction methodology with a quantum-dot cellular-automata-based approach. J Comput Electron 20, 1611–1624 (2021). https://doi.org/10.1007/s10825-021-01712-9

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