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A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET

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Abstract

We present a detailed study on the n-channel single-gate junctionless transistor (JLT) at the \({10}-\hbox{nm}\) node. We investigate the influence of its structural parameters on the on-state current and the off-state leakage current. Furthermore, we show that the use of high-k spacers may not be advantageous in future nanoscale junctionless transistors and confirm this argument by simulation. We also present the results of our investigation on process variations, including the sensitivity of the JLT to random dopant fluctuations as well as the gate work function using Monte Carlo simulations. These results are then compared with those of a conventional FinFET. Finally, we provide design guidelines for JLTs at \({10}-\hbox{nm}\) gate length.

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  1. Department of Electrical and Computer Engineering, Faculty of Engineering, University of Tehran, North Kargar Ave., Tehran, Iran

    Amin Rassekh & Morteza Fathipour

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  1. Amin Rassekh
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  2. Morteza Fathipour
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Correspondence to Morteza Fathipour.

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Rassekh, A., Fathipour, M. A single-gate SOI nanosheet junctionless transistor at 10-nm gate length: design guidelines and comparison with the conventional SOI FinFET. J Comput Electron 19, 631–639 (2020). https://doi.org/10.1007/s10825-020-01475-9

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  • DOI: https://doi.org/10.1007/s10825-020-01475-9

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