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Enhancement of the DC performance of a PNPN hetero-dielectric BOX tunnel field-effect transistor for low-power applications

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Abstract

A comparative analysis is performed on a PNPN hetero-dielectric buried oxide (BOX) tunnel field-effect transistor (FET) with the conventional versus various modified structures, including the effects of using a high-k dielectric (HfO2) below the gate electrode and/or a low-bandgap material (InAs) as a source pocket. The use of InAs as a low-bandgap material greatly improves the tunneling of charge carriers from the source to channel region in the tunnel FET. Meanwhile, technology computer-aided design (TCAD) simulations reveal that inclusion of the high-k gate oxide with InAs as the source pocket in the PNPN structure results in a huge improvement in the electrostatic characteristics of the proposed structure in terms of both the ON-state current and subthreshold swing (SS). The proposed structure achieves a SS of 4.64 mV/dec and an ON-state current density of \(1.5\times 10^{-3}\) A/\(\mu \)m.

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Authors and Affiliations

  1. RGM College of Engineering and Technology, Nandyal, Kurnool, India

    Mohd. Aslam & Shivendra Yadav

  2. Design and Manufacturing, PDPM Indian Institute of Information Technology, Jabalpur, India

    Girjesh Korram & Dheeraj Sharma

  3. Ramrao Adik Institute of Technology, Nerul, Navi Mumbai, India

    Neeraj Sharma

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  1. Mohd. Aslam
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  2. Girjesh Korram
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  3. Dheeraj Sharma
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  4. Shivendra Yadav
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Aslam, M., Korram, G., Sharma, D. et al. Enhancement of the DC performance of a PNPN hetero-dielectric BOX tunnel field-effect transistor for low-power applications. J Comput Electron 19, 271–276 (2020). https://doi.org/10.1007/s10825-019-01427-y

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