Electrostatically doped drain junctionless transistor for low-power applications

Abstract

Junctionless transistors (JLT) are a promising alternative to address the stringent junction requirements in conventional transistors. However, JLTs are plagued by high OFF-state leakage current attributed to the band-to-band tunneling at the channel–drain interface. This leakage current is often referred to as gate-induced drain leakage (GIDL). In this paper, we propose an effective technique to suppress GIDL in JLTs. We use the charge plasma concept to realize an electrostatically doped drain (EDD) separated from the channel by an intermediate intrinsic region. Therefore, the proposed EDD–JLT is an n⁺–n⁺–i–n⁺ structure that widens the tunnel barrier at the gate–drain interface in the OFF-state (V_GS = 0 V, V_DS = 1 V) and offers significant reduction in leakage current. We compare, using 2D TCAD device simulations, the EDD–JLT with the conventional JLT in terms of various digital and analog performance metrics. We observe that EDD–JLTs of gate length 20 nm offer a significant reduction in I_OFF (~ 4 orders) while substantially improving I_ON/I_OFF ratio (~ 4 orders) as compared to conventional JLTs. To study the scalability of the proposed technique, the device thickness and gate length were scaled down to 5 nm. We observe that even for scaled-down structure, EDD–JLTs retain their performance benefit. We observe that the analog performance metrics such as intrinsic gain (G_mR_o), transconductance generation factor (G_m/I_D), output conductance (G_D), channel length modulation, and drain-induced barrier lowering of EDD–JLTs are also significantly improved as compared to conventional JLTs.