Journal of Computational Electronics

, Volume 17, Issue 3, pp 967–976 | Cite as

A dopingless gate-all-around (GAA) gate-stacked nanowire FET with reduced parametric fluctuation effects

  • Sarabdeep Singh
  • Ashish Raman


This paper proposes a gate-all-around silicon nanowire dopingless field-effect transistor (FET), utilizing a gate-stacked technique. The source and drain regions are formed by employing a charge plasma concept, with the application of appropriate work functions for metal contacts. The charge plasma approach reduces the need for doping control during fabrication, and thus reduces the thermal budget, while the gate-stacked structure solves the problem of scaling limitations with respect to the \(\hbox {SiO}_{2}\) dielectric thickness (< 2 nm). The simulation results show that the proposed device, when compared with a conventional junctionless nanowire FET (JL-NWFET), possesses enhanced performance parameters, with improved immunity to short-channel effects. The random dopant fluctuations (RDFs) of the proposed device are analyzed and compared with those of a conventional JL-NWFET. The conventional device has a high doping concentration, and as a result suffers from higher RDFs, whereas the proposed dopingless device possesses lower RDFs. The process parameters used to measure sensitivity to RDFs include the radius, doping concentration and gate oxide thickness. When the radius of the nanowire is varied by \(+\) 30%, changes in threshold voltage, on-state current and subthreshold slope of 66, 63 and 12%, respectively, are observed in the JL-NWFET, versus 5, 22.6 and 1.8% for the proposed dopingless device (CP-NWFET). Similar variations in doping concentration and gate oxide thickness are seen with the JL-NWFET, whereas the CP-NWFET is largely unaffected. Thus, the proposed gate-stacked dopingless CP-NWFET solves the issue of both doping control and scaling limitation of the gate oxide layer, which paves the way for easier fabrication, with exceptional immunity against parametric variations, making it a good candidate for future nanoscale devices.


Nanowire Inversion mode Random dopant fluctuations Charge plasma Gate stack Short-channel effects 


  1. 1.
    Lu, W., Xie, P., Lieber, C.M.: Nanowire transistor performance limits and applications. IEEE Trans. Electron Devices 55(11), 2859–2876 (2008)CrossRefGoogle Scholar
  2. 2.
    Cho, S., Kim, K.R., Park, B.G., Kang, I.M.: RF performance and small-signal parameter extraction of junctionless silicon nanowire MOSFETs. IEEE Trans. Electron Devices 58(5), 1388–1396 (2011)CrossRefGoogle Scholar
  3. 3.
    Kumar, M., Haldar, S., Gupta, M., Gupta, R.S.: Impact of gate material engineering (GME) on analog/RF performance of nanowire Schottky-barrier gate all around (GAA) MOSFET for low power wireless applications: 3D T-CAD simulation. Microelectron. J. 45(11), 1508–1514 (2014)CrossRefGoogle Scholar
  4. 4.
    Sharma, S.K., Raj, B., Khosla, M.: A Gaussian approach for analytical subthreshold current model of cylindrical nanowire FET with quantum mechanical effects. Microelectron. J. 53, 65–72 (2016)CrossRefGoogle Scholar
  5. 5.
    Liu, B., Zhan, C., Yang, Y., Cheng, R., Guo, P., Zhou, Q., Kong, E.Y.J., Daval, N., Veytizou, C., Delprat, D., Nguyen, B.Y.: Germanium multiple-gate field-effect transistor with in situ boron-doped raised source/drain. IEEE Trans. Electron Devices 60(7), 2135–2141 (2013)CrossRefGoogle Scholar
  6. 6.
    Shih, C.H., Liang, J.T., Wang, J.S., Chien, N.D.: A source-side injection lucky electron model for Schottky barrier metal-oxide-semiconductor devices. IEEE Electron Device Lett. 32(10), 1331–1333 (2011)CrossRefGoogle Scholar
  7. 7.
    Colinge, J.P., Kranti, A., Yan, R., Lee, C.W., Ferain, I., Yu, R., Akhavan, N.D., Razavi, P.: Junctionless nanowire transistor (JNT): properties and design guidelines. Solid-State Electron. 65, 33–37 (2011)CrossRefGoogle Scholar
  8. 8.
    Doria, R.T., Pavanello, M.A., Trevisoli, R.D., de Souza, M., Lee, C.W., Ferain, I., Akhavan, N.D., Yan, R., Razavi, P., Yu, R., Kranti, A.: Junctionless multiple-gate transistors for analog applications. IEEE Trans. Electron Devices 58(8), 2511–2519 (2011)CrossRefGoogle Scholar
  9. 9.
    Baruah, R.K., Paily, R.P.: A dual-material gate junctionless transistor with a high-k spacer for enhanced analog performance. IEEE Trans. Electron Devices 61(1), 123–128 (2014)CrossRefGoogle Scholar
  10. 10.
    Rios, R., Cappellani, A., Armstrong, M., Budrevich, A., Gomez, H., Pai, R., Rahhal-Orabi, N., Kuhn, K.: Comparison of junctionless and conventional tri-gate transistors with Lg down to 26 nm. IEEE Electron Device Lett. 32(9), 1170–1172 (2011)CrossRefGoogle Scholar
  11. 11.
    Tan, C.M., Chen, X.: Random dopant fluctuation in gate-all-around nanowire FET. In: IEEE International Conference in Nanoelectronics, pp. 1–4 (2014)Google Scholar
  12. 12.
    Tang, X., De, V.K., Meindl, J.D.: Intrinsic MOSFET parameter fluctuations due to random dopant placement. IEEE Trans. Very Large Scale Integr. VLSI Syst. 5(4), 369–376 (1997)CrossRefGoogle Scholar
  13. 13.
    Hueting, R.J.E., Rajasekharan, B., Salm, C., et al.: Charge plasma P-N diode. IEEE Electron Device Lett. 29(12), 1367–1368 (2008)CrossRefGoogle Scholar
  14. 14.
    Rajasekharan, B., Hueting, R.J., Salm, C., van Hemert, T., Wolters, R.A., Schmitz, J.: Fabrication and characterization of the charge-plasma diode. IEEE Electron Device Lett. 31(6), 528–530 (2010)CrossRefGoogle Scholar
  15. 15.
    Kumar, M.J., Nadda, K.: Bipolar charge-plasma transistor: a novel three terminal device. IEEE Trans. Electron Devices 59(4), 962–967 (2012)CrossRefGoogle Scholar
  16. 16.
    Kumar, M.J., Janardhanan, S.: Doping-less tunnel field effect transistor: design and investigation. IEEE Trans. Electron Devices 60(10), 3285–3290 (2013)CrossRefGoogle Scholar
  17. 17.
    Anand, S., Amin, S.I., Sarin, R.K.: Analog performance investigation of dual electrode based doping-less tunnel FET. J. Comput. Electron. 15(1), 94–103 (2016)CrossRefGoogle Scholar
  18. 18.
    Sahu, C., Singh, J.: Charge-plasma based process variation immune junctionless transistor. IEEE Electron Device Lett. 35(3), 411–413 (2014)CrossRefGoogle Scholar
  19. 19.
    Intekhab Amin, S., Sarin, R.K.: Charge-plasma based dual material and gate-stacked architecture of junctionless transistor for enhanced analog performance. Superlattices Microstruct. 88, 582–590 (2015)CrossRefGoogle Scholar
  20. 20.
    Amin, S.I., Sarin, R.K.: Enhanced analog performance of doping-less dual material and gate stacked architecture of junctionless transistor with high-k spacer. Appl. Phys. A 122(4), 380 (2016)CrossRefGoogle Scholar
  21. 21.
    Lo, S.H., Buchanan, D.A., Taur, Y., Wang, W.: Quantum-mechanical modeling of electron tunneling current from the inversion layer of ultra-thin-oxide nMOSFET’s. IEEE Electron Device Lett. 18(5), 209–211 (1997)CrossRefGoogle Scholar
  22. 22.
    Cheng, B., Cao, M., Rao, R., Inani, A., Voorde, P.V., Greene, W.M., Stork, J.M., Yu, Z., Zeitzoff, P.M., Woo, J.C.: The impact of high-/spl kappa/gate dielectrics and metal gate electrodes on sub-100 nm MOSFETs. IEEE Trans. Electron Devices 46(7), 1537–1544 (1999)CrossRefGoogle Scholar
  23. 23.
    Gundapaneni, S., Ganguly, S., Kottantharayil, A.: Enhanced electrostatic integrity of short-channel junctionless transistor with high-k spacers. IEEE Electron Device Lett. 32(10), 1325–1327 (2011)CrossRefGoogle Scholar
  24. 24.
    Sahay, S., Kumar, M.J.: Diameter dependence of leakage current in nanowire junctionless field effect transistors. IEEE Trans. Electron Devices 64(3), 1330–1335 (2017)CrossRefGoogle Scholar
  25. 25.
    ATLAS Device Simulation Software: Silvaco International. Santa Clara, CA, USA (2014)Google Scholar
  26. 26.
    Singh, N.K., Raman, A., Singh, S., Kumar, N.: A novel high mobility In1\(-\)x Gax As cylindrical-gate-nanowire FET for gas sensing application with enhanced sensitivity. Superlattices Microstruct. 111, 518–528 (2017)CrossRefGoogle Scholar
  27. 27.
    Trivedi, N., Kumar, M., Haldar, S., Deswal, S.S., Gupta, M., Gupta, R.S.: Charge plasma technique based dopingless accumulation mode junctionless cylindrical surrounding gate MOSFET: analog performance improvement. Appl. Phys. A 123(9), 564 (2017)CrossRefGoogle Scholar
  28. 28.
    Boucart, K., Ionescu, A.M.: Double-gate tunnel FET with high-k gate dielectric. IEEE Trans. Electron Devices 54(7), 1725–1733 (2007)CrossRefGoogle Scholar

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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  1. 1.Department of Electronics and Communication EngineeringNIT JalandharJalandharIndia

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