Journal of Computational Electronics

, Volume 17, Issue 2, pp 613–624 | Cite as

The effect of sharp-corner emendation of irregular FinFETs on electrothermal characteristics

  • Fa. Karimi
  • Ali A. Orouji


The present study is an attempt to investigate the impacts of channel modification and the capabilities of amended sharp-corner FinFETs from thermal and electrical points of view. It also provides a new definition for gate-oxide and channel capacitance of irregular fin shape by replacing the contribution of each area in the total gate capacitance expression of the square FinFET. This definition determines the subthreshold reliability of the amended sharp-corner FinFETs. As a function of gate insulator capacitance, channel capacitance, depletion charge per unit length, and fin area, mobile electron concentrations are derived for amended sharp-corner FETs by assuming an arbitrary channel potential profile to simplify the formulation. The comparison results demonstrate that an amended FinFET with a partial cylindrical shape at the top region of fin (PC-FinFET) by higher gate controllability adjusts the hot carrier effects, reduces DIBL, improves the subthreshold characteristics as well as short-channel effects, while the amended-channel FinFET with extended round-bottom region reduces the self-heating effects, attenuates the thermal resistance, and moderates the thermal dependence of electrical characteristics. Therefore, it is deduced that modified-channel FinFET (MC-FinFET), with both cylindrical top and extended bottom regions, has improved thermal and electrical stabilities in both subthreshold and saturation modes in comparison with a conventional thin-film FinFET. The superiority of the MC-FinFET, which was evaluated with three-dimensional simulations, demonstrates the ability of this structure as a high-performance device over the other eliminated sharp-corner FinFETs.


Sharp corners Hot carriers Self-heating Short-channel behavior Thermal stability FinFET Non-rectangular Irregular fin 


  1. 1.
    Hisamoto, D., Lee, W.-C., Kedzierski, J., Takeuchi, H., Asano, K., Kuo, C., Anderson, E., King, T.-J., Bokor, J., Chenming, H.: FinFET—a self-aligned double-gate MOSFET scalable to 20 nm. IEEE Trans. Electron Devices 47(12), 2320–2325 (2000)CrossRefGoogle Scholar
  2. 2.
    Choi, J.A., Kwon, L., You, S.J., Lee, Y.-J., Soo, Y.L., Geon, U.L., Lee, S.-H., Min, C.S., Kim, D.-C., Young, M.L., Su, G.B., Yang, J.-H., Shigenobu, M., Lee, N., Kang, H., Suh, K.-P.: Large scale integration and reliability consideration of triple gate transistors. In: IEEE Technical Digest of International Electron Devices Meeting (IEDM), pp. 647–650 (2004)Google Scholar
  3. 3.
    Yu, Z., Chang, S., Wang, H., He, J., Huang, Q.: Effects of Fin shape on sub-10 nm FinFETs. J. Comput. Electron. 14, 515–523 (2015)CrossRefGoogle Scholar
  4. 4.
    Abraham, D., George, A., Gopinadh, D.: Effect of Fin shape on GIDL and subthreshold leakage currents. Int. J. Sci. Technol. Eng. 1(10), 135–145 (2015)Google Scholar
  5. 5.
    Anand, Sunny, Sarin, R.K.: An analysis on Am bipolar reduction techniques for charge plasma based tunnel field effect transistors. J. Nanoelectron. Optoelectron. 11(4), 543–550 (2016)CrossRefGoogle Scholar
  6. 6.
    Anand, Sunny, Sarin, R.K.: Analog and RF performance of doping-less tunnel FETs with \(\text{ Si }_ {0.55}\text{ Ge }_{0.45}\) source. J. Comput. Electron. 15(3), 850–856 (2016)CrossRefGoogle Scholar
  7. 7.
    Ritzehnthaler, R., Faynot, O., Jahan, C., Kuriyama, A., Deleonibus, S., Cristoloveanu, S.: Coupling effects in FinFETs and triple-gate FETs. In: Proceedings of the 7th European Workshop ULIS, pp. 25–28 (2006)Google Scholar
  8. 8.
    Ruiz, F.J.G., Godoy, A., Gámiz, F., Sampedro, C., Donetti, L.: A comprehensive study of the corner effects in Pi-gate MOSFETs including quantum effects. IEEE Trans. Electron Devices 54(12), 3369–3377 (2007)CrossRefGoogle Scholar
  9. 9.
    Fossum, J.G., Yang, J.-W., Trivedi, V.P.: Suppression of corner effects in triple-gate MOSFETs. IEEE Electron Devices Lett. 24(12), 745–747 (2003)CrossRefGoogle Scholar
  10. 10.
    Collaert, N., et al.: Multi-gate devices for the 32 nm technology node and beyond. Solid State Electron. 52(9), 1291–1296 (2008)CrossRefGoogle Scholar
  11. 11.
    Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.: Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans. Electron Devices 52(6), 1132–1140 (2005)CrossRefGoogle Scholar
  12. 12.
    Lederer, D., Parvais, B., Mercha, A., Collaert, N., Jurczak, M., Raskin, J.-P., Decoutere, S.: Dependence of FinFET RF performance on fin width. In: Proceedings of the 6th Topical Meeting Silicon Monolithic Integrated Circuits RF System, SiRF, pp. 8–11 (2006)Google Scholar
  13. 13.
    Auth, C. et al.: A 22 nm high performance and low-power CMOS technology featuring fully-depleted tri-gate transistors, self-aligned contacts and high density MIM capacitors. In: Proceedings of the IEEE Symposium on Very Large Scale Integrated System (VLSI) Technology, pp. 131–132 (2012)Google Scholar
  14. 14.
    Han, K.-R., Choi, B.-K., Kwon, H.-I., Lee, J.-H.: Design of bulk Fin-type field-effect transistor considering gate work-function. Jpn. J. Appl. Phys. 47(6R), 4385–4391 (2008)CrossRefGoogle Scholar
  15. 15.
    Tawfik, S.A., Kursun, V.: Multi-threshold voltage FinFET sequential circuits. IEEE Trans. Very Large Scale Integr. Syst. 19(1), 151–156 (2011)CrossRefGoogle Scholar
  16. 16.
    Sheu, B.J. et al.: Enabling circuit design using FinFETs through close ecosystem collaboration. In: Proceedings of the Symposium on Very Large Scale Integrated (VLSI) Technology, pp. T110–T111 (2013)Google Scholar
  17. 17.
    Lin, C.-H. et al.: Channel doping impact on FinFETs for 22 nm and beyond. In: Proceedings of the Symposium on Very Large Scale Integrated (VLSI) Technology, pp. 15–16 (2012)Google Scholar
  18. 18.
    Wu, Xusheng, Chan, Philip C.H., Chan, Mansun: Impacts of nonrectangular fin cross section on the electrical characteristics of FinFET. IEEE Trans. Electron Devices 52(1), 63–68 (2005)CrossRefGoogle Scholar
  19. 19.
    Giacomini, R., Martino, J.A.: Trapezoidal cross-sectional influence on FinFET threshold voltage and corner effects. J. Electrochem. Soc. 155(4), H213–H217 (2008)CrossRefGoogle Scholar
  20. 20.
    Liu, Y., et al.: Cross-sectional channel shape dependence of short-channel effects in fin-type double-gate metal oxide semiconductor field-effect transistors. Jpn. J. Appl. Phys. 43(4B), 2151–2155 (2004)CrossRefGoogle Scholar
  21. 21.
    Buhler, R.T., Martino, J.A., Agopian, P.G.D., Giacomini, R., Simoen, E., Claeys, C.: Fin shape influence on the analog performance of standard and strained MuGFETs. In: IEEE International on SOI Conference (SOI), San Diego, vol. 1–2 (2010)Google Scholar
  22. 22.
    Mehrad, M., Orouji, A.A.: A new nanoscale and high temperature field effect transistor: Bi level FinFET. Physica E 44, 654 (2011)CrossRefGoogle Scholar
  23. 23.
    Mehrad, M., Orouji, A.A.: Partially cylindrical fin field-effect transistor: a novel device for nanoscale applications. IEEE Trans. Device Mater. Reliab. 10, 271 (2010)CrossRefGoogle Scholar
  24. 24.
    Karimi, Fa, Orouji, A.A.: A novel nanoscale fin field effect transistor by amended channel: investigation and fundamental physics. Physica E 74, 65 (2015)CrossRefGoogle Scholar
  25. 25.
    Karimi, Fa, Orouji, A.A.: Electro-thermal analysis of non-rectangular FinFET and modeling of fin shape effect on thermal resistance. Physica E 90, 218 (2017)CrossRefGoogle Scholar
  26. 26.
    Kretz, J., Dreeskornfeld, L., Schroter, R., Landgraf, E., Hofmann, F., Ro sner, W.: Realization and characterization of nano-scale FinFET devices. Solid State Micro Electron. Eng. 73, 803 (2004)Google Scholar
  27. 27.
    Okano, K. et al.: Process integration technology and device characteristics of CMOS FinFET on bulk silicon substrate with sub-10 nm fin width and 20 nm gate length. In: Electron Devices Meeting, 2005. IEDM Technical Digest. IEEE International, 2005, pp. 721–724, IEEEGoogle Scholar
  28. 28.
    Jiménez, D., Saenz, J.J., Iñiguez, B., Suñé, J., Marsal, L.F., Pallares, J.: Modeling of nanoscale gate-all-around MOSFETs. IEEE Electron Device Lett. 25(5), 314–316 (2004)CrossRefGoogle Scholar
  29. 29.
    Ruiz, F., Tienda-Luna, I., Godoy, A., Donetti, L., Gamiz, F.: Equivalent oxide thickness of trigate SOI MOSFETs with high-kappa insulators. IEEE Trans. Electron Devices 56(11), 2711–2719 (2009)CrossRefGoogle Scholar
  30. 30.
    Chen, T.: Determination of the capacitance, inductance, and characteristic impedance of rectangular lines. IRE Trans. Microw. Theory Tech. 8(5), 510–519 (1960)CrossRefGoogle Scholar
  31. 31.
    Tienda-Luna, I.M., Ruiz, F.J.G., Donetti, L., Godoy, A., Gámiz, F.: Modeling the equivalent oxide thickness of surrounding gate SOI devices with high-\(\kappa \) insulators. Solid State Electron. 52(12), 1854–1860 (2008)CrossRefGoogle Scholar
  32. 32.
    Duarte, J.P., Choi, S., Moon, D., Ahn, J., Kim, J., Kim, S., Choi, Y.: A universal core model for multiple-gate field-effect transistors. Part I: charge model. IEEE Trans. Electron Devices 60(2), 840–847 (2013)CrossRefGoogle Scholar
  33. 33.
    Dunga, M.: Nanoscale CMOS Modeling. University of California, Berkeley (2008)Google Scholar

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Authors and Affiliations

  1. 1.Electrical and Computer Engineering DepartmentSemnan UniversitySemnanIran

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