Journal of Computational Electronics

, Volume 17, Issue 2, pp 713–723 | Cite as

Two-dimensional (2D) analytical investigation of an n-type junctionless gate-all-around tunnel field-effect transistor (JL GAA TFET)

  • Ajay
  • Rakhi Narang
  • Manoj Saxena
  • Mridula Gupta


Tunnel field-effect transistors have shown great potential given their good scalability and low leakage current. However, they are associated with some drawbacks, including ambipolar behavior and low ON-state current relative to the MOSFET. To overcome these problems, a novel junctionless gate-all-around TFET (JL GAA TFET) is proposed. The proposed device employs a two-dimensional model by solving Poisson’s equation in 2D. The results are verified with the assistance of Sentaurus Device simulation software. The electrical and electrostatic characteristics of the JL GAA TFET, including its surface potential, energy band, electric field, threshold voltage and drain current, are studied using models and simulations. The impact of various gate insulator materials is also studied using the model, and the transfer current of the JL GAA TFET is compared with that of a different type of FET device. The JL GAA TFET exhibits a high \(I_{\mathrm{ON}}/I_{\mathrm{OFF}}\) ratio (\(\sim 10^{9}\)) and a subthreshold slope of 28 mV/decade at room temperature for the high-kdielectric gate insulator material \((\hbox {TiO}_{2})\). With regard to the use of the device in switching applications, the JL GAA TFET appears to be a good candidate.


Analytical model Gate-all-around Junctionless Subthreshold slope (SS) TCAD Tunnel FET 



The authors would like to thank the University of Delhi, New Delhi, India, for providing the necessary financial assistance during the course of this research. Ajay would like to thank Advanced Nanoelectronics Computation Laboratory, Department of Electronics System Engineering, Indian Institute of Science, Bangalore, India.


Funding was provided by University Grant Commission of India [(Grant No. 4009/(NET JUNE 2013)].


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© Springer Science+Business Media, LLC, part of Springer Nature 2018

Authors and Affiliations

  • Ajay
    • 1
  • Rakhi Narang
    • 2
  • Manoj Saxena
    • 3
  • Mridula Gupta
    • 4
  1. 1.Advanced Nanoelectronics Computation LaboratoryIndian Institute of ScienceBangaloreIndia
  2. 2.Department of ElectronicsSri Venkateswara College, University of DelhiNew DelhiIndia
  3. 3.Department of ElectronicsDeen Dayal Upadhyaya College, University of DelhiNew DelhiIndia
  4. 4.Semiconductor Device Research Laboratory, Department of Electronic ScienceUniversity of DelhiNew DelhiIndia

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