Journal of Computational Electronics

, Volume 16, Issue 4, pp 1257–1269 | Cite as

Review of physics-based compact models for emerging nonvolatile memories

  • Nuo XuEmail author
  • Pai-Yu Chen
  • Jing Wang
  • Woosung Choi
  • Keun-Ho Lee
  • Eun Seung Jung
  • Shimeng Yu
S.I. : Computational Electronics of Emerging Memory Elements


A generic compact modeling methodology for emerging nonvolatile memories is proposed by coupling comprehensive physical equations from multiple domains (e.g., electrical, thermal, magnetic, phase transitions). This concept has been applied to three most promising emerging memory candidates: PCM, STT-MRAM, and RRAM to study their device physics as well as to evaluate their circuit-level performance. The models’ good predictability to experiments and their effectiveness in large-scale circuit simulation suggest their unique role in emerging memory research and development.


Compact modeling Nonvolatile memory (NVM ) Reaction rate equation (RRE ) GST PCM OTS STT-MRAM RRAM Cross-point 1T1R 



N. Xu, J. Wang and W. Choi would like to thank the contribution from U. Monga, S.-C. Lee, J. Jeon, S. Ahn, Y. Lu, B. Fu, H.-H. Park, D. Apalkov from Samsung Electronics Ltd. and Y. Deng from Purdue University. P.-Y. Chen and S. Yu would like to thank for the support from NSF CCF-1449653.


  1. 1.
    Yu, S., Chen, P.-Y.: Emerging memory technologies: recent trends and prospects. IEEE Solid State Circuits Mag. 8(2), 43–56 (2016)CrossRefGoogle Scholar
  2. 2.
    Ovshinsky, S.R.: Reversible electrical switching phenomena in disordered structures. Phys. Rev. Lett. 21(20), 1450–1455 (1968)CrossRefGoogle Scholar
  3. 3.
    Wong, H.-S.P., et al.: Phase change memory. Proc. IEEE 98(12), 2201–2227 (2010)CrossRefGoogle Scholar
  4. 4.
    Lai, S.: Current status of the phase change memory and its future. In: IEEE International Electron Device Meeting (IEDM), 10.1 (2003)Google Scholar
  5. 5.
    Burr, G.W., et al.: Overview of candidate device technologies for storage-class memory. IBM J. Res. Dev. 52(4), 449–464 (2008)CrossRefGoogle Scholar
  6. 6.
    Song, Y.J., et al.: Highly reliable 256 Mb PRAM with advanced ring contact technology and novel encapsulating technology. In: IEEE symposium on VLSI technology, pp. 118–119 (2006)Google Scholar
  7. 7.
    Tehrani, S., et al.: Magnetoresistive random access memory using magnetic tunnel junctions. Proc. IEEE 91, 703–714 (2003)CrossRefGoogle Scholar
  8. 8.
    Albrecht, T.R., et al.: Bit-patterned magnetic recording: theory, media fabrication, and recording performance. IEEE Trans. Magn. 51(5), 0800342 (2015)CrossRefGoogle Scholar
  9. 9.
    Slonczewski, J.C.: Current-driven excitation of magnetic multilayers. J. Magn. Magn. Mater. 159, L1–7 (1996)CrossRefGoogle Scholar
  10. 10.
    Berger, L.: Emission of spin waves by a magnetic multilayer traversed by a current. Phys. Rev. B 54, 9353–9358 (1996)CrossRefGoogle Scholar
  11. 11.
    Katine, J., et al.: Current-driven magnetization reversal and spin-wave excitations in Co/Cu/Co pillars. Phys. Rev. Lett. 84, 3149–3152 (2000)CrossRefGoogle Scholar
  12. 12.
    Chen, E., et al.: Advances and future prospects of spin-transfer torque random access memory. IEEE Trans. Magn. 46(6), 1873–1878 (2010)CrossRefGoogle Scholar
  13. 13.
    Yoda, H., et al.: Progress of STT-MRAM technology and the effect on normally-off computing systems. In: IEEE International Electron Device Meeting (IEDM), pp. 259–262 (2012)Google Scholar
  14. 14.
    Watanabe, Y., et al.: Current-driven insulator–conductor transition and nonvolatile memory in chromium-doped SrTiO\(_{3}\) single crystals. Appl. Phys. Lett. 78, 3738–3740 (2001)CrossRefGoogle Scholar
  15. 15.
    Wong, H.S.-P., et al.: Metal-oxide RRAM. Proc. IEEE 100(6), 1951–1970 (2012)CrossRefGoogle Scholar
  16. 16.
    Waser, R., et al.: Nanoionics-based resistive switching memories. Nat. Mater. 6(11), 833–840 (2007)CrossRefGoogle Scholar
  17. 17.
    Xu, N., et al.: Characteristics and mechanism of conduction/set process in TiN/ZnO/Pt resistance switching random-access memories. Appl. Phys. Lett. 92(23), 232112 (2008)CrossRefGoogle Scholar
  18. 18.
    The Vienna Ab Initio Simulation Package (VASP).
  19. 19.
    LAMMPS Molecular Dynamics Simulator, Sandia National Labs.
  20. 20.
    The Object Oriented MicroMagnetic Framework (OOMMF), NIST.
  21. 21.
    Gao B., et al.: Oxide-based RRAM switching mechanism: a new ion-transport-recombination model. In: IEEE International Electron Devices Meeting (IEDM). (2008)Google Scholar
  22. 22.
    Makarov, A., et al.: Stochastic modeling hysteresis and resistive switching in bipolar oxide-based memory. In: IEEE Simulation of Semiconductor Devices and Process (SISPAD), pp. 237–240 (2010)Google Scholar
  23. 23.
    Lu, D.: Compact models for future generation CMOS. University of California, Berkeley, Ph.D. Thesis (2011)Google Scholar
  24. 24.
    Simulation Program with Integrated Circuit Emphasis (SPICE), University of California, Berkeley, (1973)Google Scholar
  25. 25.
    Toshiyoshi H., et al.: A multi-physics simulation technique for integrated MEMS. In: IEEE International Electron Devices Meeting (IEDM), pp. 123–126 (2012)Google Scholar
  26. 26.
    An RRE is a Langevin equation without the Gaussian white noise term. Refer to P. Langevin, On the Theory of Brownian Motion, C. R. Acad. Sci., 146, pp. 530–533 (1908)Google Scholar
  27. 27.
    Wang, T., et al.: Well-posed models of memristive devices. arXiv:1605.04897v1. (2016)
  28. 28.
    Ielmini, D., et al.: Analytical model for subthreshold conduction and threshold switching in chalcogenide-based memory devices. J. Appl. Phys. 102, 054517 (2007)CrossRefGoogle Scholar
  29. 29.
    Ventrice, D., et al.: A phase change memory compact model for multilevel applications. IEEE Electron Dev. Lett. 28(11), 973–975 (2007)CrossRefGoogle Scholar
  30. 30.
    Chen, I.-R., et al.: Compact thermal model for vertical nanowire phase-change memory cells. IEEE Trans. Electron Dev. 56(7), 1523–1528 (2009)CrossRefGoogle Scholar
  31. 31.
    Xu, N., et al.: Multi-domain compact modeling for GeSbTe-based memory and selector devices and simulation for large-scale 3-D cross-point memory arrays. In: IEEE International Electron Device Meeting (IEDM), pp. 192–195 (2015)Google Scholar
  32. 32.
    Anbarasu, M., et al.: Nanosecond threshold switching of GeTe\(_{6}\) cells and their potential as selector devices. Appl. Phys. Lett. 100, 143505 (2012)CrossRefGoogle Scholar
  33. 33.
    Schmithusen, B., et al.: Phase-change memory simulations using an analytical phase space model. IEEE Simulation of Semiconductor Devices and Process (SISPAD), 3.6.1 (2008)Google Scholar
  34. 34.
    Radaelli, A., et al.: Threshold switching and phase transition numerical models for phase change memory simulations. J. Appl. Phys. 103, 111101 (2008)CrossRefGoogle Scholar
  35. 35.
    Peng, C., et al.: Experimental and theoretical investigations of laser-induced crystallization and amorphization in phase-change optical recording media. J. Appl. Phys. 82, 4183–4191 (1997)CrossRefGoogle Scholar
  36. 36.
    Senkadar, S., et al.: Model for phase-change of Ge\(_{2}\)Sb\(_{2}\)Te\(_{5}\) in optical and electrical memory devices. J. Appl. Phys. 95, 504–511 (2004)CrossRefGoogle Scholar
  37. 37.
    Zhang, L., et al.: One-selector one-resistor cross-point array with threshold switching selector. IEEE Trans. Electron Dev. 62(10), 3250–3257 (2015)CrossRefGoogle Scholar
  38. 38.
    International Technology Roadmap for Semiconductors (ITRS), 2014 editionGoogle Scholar
  39. 39.
    Kim, S.-B., et al.: Thermal disturbance and its impact on reliability of phase-change memory studied by the micro-thermal stage. In: IEEE Reliability Physics Symposium, pp. 99–103 (2010)Google Scholar
  40. 40.
    Panagopoulos, G.D., et al.: Physics-based SPICE-compatible compact model for simulating hybrid MTJ/CMOS circuits. IEEE Trans. Electron Dev. 60(9), 2808–2814 (2013)CrossRefGoogle Scholar
  41. 41.
    Fong, X.: et al.: KNACK: a hybrid spin-charge mixed-mode simulator for evaluating different genres of spin-transfer torque MRAM bit-cells. In: IEEE simulation of semiconductor devices and process (SISPAD), pp. 51–54 (2011)Google Scholar
  42. 42.
    Kazemi, M., et al.: Adaptive compact magnetic tunnel junction model. IEEE Trans. Electron Dev. 61(11), 3883–3891 (2014)CrossRefGoogle Scholar
  43. 43.
    Madec, M., et al.: Compact modeling of a magnetic tunnel junction—Part II: tunneling current model. IEEE Trans. Electron Dev. 57(6), 1416–1424 (2010)CrossRefGoogle Scholar
  44. 44.
    Xu, N.: et al.: Physics-based compact modeling framework for state-of-the-art and emerging STT-MRAM technology. In: IEEE international electron device meeting (IEDM), pp. 735–738 (2015)Google Scholar
  45. 45.
    Kim, J.-H., et al.: Verification on the extreme scalability of STT-MRAM without loss of thermal stability below 15 nm MTJ cell. In: IEEE symposium on VLSI technology, pp. 60–61 (2014)Google Scholar
  46. 46.
    Slonczewski, J.C.: Conductance and exchange coupling of two ferromagnets separated by a tunneling barrier. Phys. Rev. B 39, 6995–7002 (1989)CrossRefGoogle Scholar
  47. 47.
    Brinkman, W.F., et al.: Tunneling conductance of asymmetrical barriers. J. Appl. Phys. 41, 1915–1921 (1970)CrossRefGoogle Scholar
  48. 48.
    Hiramatsu, Y., et al.: NEGF simulation of spin-transfer torque in magnetic tunnel junctions. In: IMFEDK, pp. 102–103 (2011)Google Scholar
  49. 49.
    Zhu, Z.-G., et al.: Effect of spin-flip scattering on electrical transport in magnetic tunnel junctions. Phys. Lett. A 300, 658–665 (2002)CrossRefGoogle Scholar
  50. 50.
    Beleggia, M., et al.: Demagnetization factors for elliptic cylinders. J. Phys. D 38, 3333–3342 (2005)CrossRefGoogle Scholar
  51. 51.
    Khalkovski, A.V., et al.: Basic principles of STT-MRAM cell operation in memory arrays. J. Phys. D 46, 074001 (2013)CrossRefGoogle Scholar
  52. 52.
    Guan, X., et al.: A SPICE compact model of metal oxide resistive switching memory with variations. IEEE Electron Dev. Lett. 33(10), 1405–1407 (2012)CrossRefGoogle Scholar
  53. 53.
    Huang, P., et al.: A physics-based compact model of metal-oxide-based RRAM DC and AC operations. IEEE Trans. Electron Dev. 60(12), 4090–4097 (2013)CrossRefGoogle Scholar
  54. 54.
    Bocquet, M., et al.: Robust compact model for bipolar oxide-based resistive switching memories. IEEE Trans. Electron Dev. 61(3), 674–681 (2014)CrossRefGoogle Scholar
  55. 55.
    Chen, P.-Y., et al.: Compact modeling of RRAM devices and its applications in 1T1R and 1S1R array design. IEEE Transactions on Electron Devices, vol. 62, no. 12, pp. 4022–4028 (2015).
  56. 56.
    Chen, Y.Y., et al.: Balancing SET/RESET pulse for endurance in 1T1R bipolar RRAM. IEEE Trans. Electron Dev. 59(12), 3243–3249 (2012)CrossRefGoogle Scholar
  57. 57.
    Chen, Y.Y., et al.: Improvement of data retention in HfO\(_{2}\)/Hf 1T1R RRAM cell under low operating current. In: IEEE International Electron Devices Meeting (IEDM), pp. 252–255 (2013)Google Scholar
  58. 58.
    Xu, N., et al.: A unified physical model of switching behavior in oxide-based RRAM. In: IEEE Symposium on VLSI Technology, pp. 100–101 (2008)Google Scholar
  59. 59.
    Fantini, A., et al.: Intrinsic switching variability in HfO\(_{2}\) RRAM. IEEE International Memory Workshop (IMW), pp. 30–33 (2013)Google Scholar
  60. 60.
    Yu, S., et al.: A neuromorphic visual system using RRAM synaptic devices with sub-pJ energy and tolerance to variability: experimental characterization and large-scale modeling. In: IEEE International Electron Device Meeting (IEDM), pp. 239–242 (2012)Google Scholar
  61. 61.
    Predictive Technology Model (PTM), Arizona State University.
  62. 62.
    Yalon, E., et al.: Thermometry of filamentary RRAM devices. IEEE Trans. Electron Dev. 62(9), 2972–2977 (2015)CrossRefGoogle Scholar
  63. 63.
    Guan, X., et al.: On the switching parameter variation of metal oxide RRAM—part I: physical modeling and simulation methodology. IEEE Trans. Electron Dev. 59(4), 1172–1182 (2012)CrossRefGoogle Scholar
  64. 64.
    Boniardi, M., et al.: A physics-based model of electrical conduction decrease with time in amorphous Ge\(_{2}\)Sb\(_{2}\)Te\(_{5}\). J. Appl. Phys. 105, 084506 (2009)CrossRefGoogle Scholar
  65. 65.
    Chien, W.C., et al.: Reliability study of a 128 Mb phase-change memory chip implemented with doped Ga–Sb–Ge with extraordinary thermal stability. In: IEEE international electron devices meeting (IEDM), pp. 552–555 (2016)Google Scholar
  66. 66.
    Zhang, S.: Spin hall effect in the presence of spin diffusion. Phys. Rev. Lett. 85, 393–396 (2000)CrossRefGoogle Scholar
  67. 67.
    Ciocchini, N., et al.: Impact of thermoelectric effects on phase change memory characteristics. IEEE Trans. Electron Dev. 62(10), 3264–3271 (2015)CrossRefGoogle Scholar
  68. 68.
    Hsu, C.W., et al.: Homogeneous barrier modulation of TaO\(_{x}\)/TiO\(_{2}\) bilayer for ultra-high endurance three-dimensional storage-class memory. Nanotechnology 25, 165202 (2014)CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media, LLC 2017

Authors and Affiliations

  1. 1.Device LabSamsung Semiconductor Inc.San JoseUSA
  2. 2.School of ECEEArizona State UniversityTempeUSA
  3. 3.Semiconductor R&D CenterSamsung ElectronicsHwasung-siKorea

Personalised recommendations