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Design and analysis of a gate-all-around CNTFET-based SRAM cell

Journal of Computational Electronics volume 17, pages 138–145 (2018)Cite this article

Abstract

This paper proposes a highly stable and low power 6-T static random access memory (SRAM) cell design using a gate-all-around carbon nanotube field effect transistor (GAA-CNTFET). The 6-T SRAM cell is designed and analyzed in HSPICE for different performance metrics viz. SNM, read SNM, write SNM, delay, and leakage power for both the top gate CNTFET and the GAA-CNTFET. The effect of variation of the power supply voltage on the leakage current is also presented, and it was found that the GAA-CNTFET accounts for low power dissipation at higher supply voltage. The 6-T SRAM cell is analyzed for different flat band conditions of the p-type CNTFET taking flatband of the n-type as constant, which is called a dual flat band voltage technique. Through simulations, it is found that by increasing the flatband voltage of a p-type CNTFET, the SRAM gives better performance. The dual flatband variation technique is compared with dual chirality technique, and it is observed that both techniques give the same results.

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Authors and Affiliations

  1. Department of Electronics and Communication, National Institute of Technology, Jalandhar, Punjab, 144011, India

    G. Saiphani Kumar, Amandeep Singh & Balwinder Raj

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  1. G. Saiphani Kumar
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  2. Amandeep Singh
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  3. Balwinder Raj
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Correspondence to Amandeep Singh.

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Saiphani Kumar, G., Singh, A. & Raj, B. Design and analysis of a gate-all-around CNTFET-based SRAM cell. J Comput Electron 17, 138–145 (2018). https://doi.org/10.1007/s10825-017-1056-x

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  • DOI: https://doi.org/10.1007/s10825-017-1056-x

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