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Journal of Computational Electronics

, Volume 15, Issue 4, pp 1424–1439 | Cite as

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

  • Zia Abbas
  • Mauro Olivieri
  • Andreas Ripp
Article
  • 149 Downloads

Abstract

We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.

Keywords

Yield Circuit sizing CMOS Statistical variations NBTI Leakage Delay 

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Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Information Engineering, Electronics and TelecommunicationSapienza University of RomeRomeItaly
  2. 2.MunEDA GmbHMunichGermany

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