Journal of Computational Electronics

, Volume 15, Issue 4, pp 1424–1439 | Cite as

Yield-driven power-delay-optimal CMOS full-adder design complying with automotive product specifications of PVT variations and NBTI degradations

  • Zia Abbas
  • Mauro Olivieri
  • Andreas Ripp


We present the detailed results of the application of mathematical optimization algorithms to transistor sizing in a full-adder cell design, to obtain the maximum expected fabrication yield. The approach takes into account all the fabrication process parameter variations specified in an industrial PDK, in addition to operating condition range and NBTI aging. The final design solutions present transistor sizing, which depart from intuitive transistor sizing criteria and show dramatic yield improvements, which have been verified by Monte Carlo SPICE analysis.


Yield Circuit sizing CMOS Statistical variations NBTI Leakage Delay 


  1. 1.
    Shams, A.M., Darwish, T.K., Bayoumi, M.A.: Performance analysis of low-power 1-bit CMOS full adder cells. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 10(1), 20–29 (2002)CrossRefGoogle Scholar
  2. 2.
    Dokania, V., Islam, A.: Circuit-level design technique to mitigate impact of process, voltage and temperature variations in complementary metal-oxide semiconductor full adder cells. IET Circuits Devices Syst. 9(3), 204–212 (2015)CrossRefGoogle Scholar
  3. 3.
    Abbas, Z., Khalid, U., Olivieri, M., Ripp, A., Pronath, M.: Optimal NBTI Degradation and PVT Variation Resistant Device Sizing in a Full Adder Cell. In: 4th International Conference on Reliability, Infocom Technologies and Optimization (ICRITO) 2015Google Scholar
  4. 4.
    Abbas, Z., Olivieri, M.: Optimal transistor sizing for maximum yield in variation aware standard cell design. Int. J. Circuit Theory Appl. 44, 1400–1424 (2016)CrossRefGoogle Scholar
  5. 5.
    Bhunia, S., Mukhopadhya, S.: Low Power Variation-Tolerant Design in Nanometer Silicon. Springer, New York (2011)CrossRefGoogle Scholar
  6. 6.
    Jaffari, J., Anis, M.: Statistical thermal profile considering process variations: analysis and applications. IEEE Trans Comput-Aided Des Integr Circuits Syst 27(6), 1027–1040 (2008)CrossRefGoogle Scholar
  7. 7.
    Grasser, T., Rott, K., Reisinger, H., Waltl, M., Schanovsky, F., Kaczer, B.: NBTI in nanoscale MOSFETs-the ultimate modeling benchmark. IEEE Trans. Electron Devices 61(11), 3586–3593 (2014)CrossRefGoogle Scholar
  8. 8.
    McConaghy, T., Dyck, K.B., Gupta, A.: Variation-Aware Design of Custom Integrated Circuits: A Hands-on Field Guide. Springer, New York (2013)CrossRefGoogle Scholar
  9. 9.
    Agarwal, K., Nassif, S.: Characterizing process variation in nanometer CMOS. In: Design Automation Conference, pp. 396–399 (2007)Google Scholar
  10. 10.
    Alam, M.A., Mahapatra, S.: A comprehensive model of PMOS NBTI degradation. Microelectron. Reliab. 45(1), 71 (2005)CrossRefGoogle Scholar
  11. 11.
    Paterna, F., Benini, L., Acquaviva, A., Papariello, F., Desoli, G., Olivieri, M.: Adaptive idleness distribution for non-uniform aging tolerance in multiprocessor systems-on-chip. Conference on Design, Automation and Test in Europe (DATE ’09). Leuven, Belgium, pp. 906–909 (2009)Google Scholar
  12. 12.
    Tudor, B., Wang, J., Chen, Z., Tan, R., Liu, W., Lee, F.: An accurate and scalable MOSFET aging model for circuit simulation. In: Proceedings of 12th International Symposium on Quality Electronic Design, pp. 1–4 (2011)Google Scholar
  13. 13.
    Tudor, B., Wang, J., Sun, C., Chen, Z., Liao, Z., Tan, R., Liu, W., Lee, F.: MOSRA: an efficient and versatile MOS aging modeling and reliability analysis solution for 45 nm and below. In: Proceedings of 10th IEEE international conference solid-state integrated circuit technology, pp. 1645–1647 (2010)Google Scholar
  14. 14.
    Jacobs, E., Berkelaar, M.R.C.M.: Gate sizing using a statistical delay model. In: Proceedings of design, automation, and test in Europe, Paris, pp. 283–290 (2000)Google Scholar
  15. 15.
    Beg, A.: Automating the sizing of transistors in CMOS gates for low-power and high noise margin operation. Int. J. Circuit Theory Appl. 43(11), 1637–1654 (2014)CrossRefGoogle Scholar
  16. 16.
    Chopra, K., Shah, S., Srivastava, A., Blaauw, D., Sylvester, D.: Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation. In: Proceedings of the IEEE/ACM international conference on computer-aided design, San Jose, pp. 1023–1028 (2005)Google Scholar
  17. 17.
    Choi, S.H., Paul, B.C., Roy, K.: Novel sizing algorithm for yield improvement under process variation in nanometer technology. In: Proceedings of the ACM/IEEE design automation conference, San Diego, pp. 454–459 (2004)Google Scholar
  18. 18.
    Sinha, D., Shenoy, N.V., Zhou, H.: Statistical gate sizing for timing yield optimization. In: Proceedings of the IEEE/ACM international conference on computer-aided design, San Jose, pp. 1037–1042 (2005)Google Scholar
  19. 19.
    Agarwal, A., Chopra, K., Blaauw, D., Zolotov, V.: Circuit optimization using statistical static timing analysis. In: Proceedings of the ACM/IEEE design automation conference, Anaheim, pp. 338–342 (2005)Google Scholar
  20. 20.
    Singh, J., Nookala, V., Luo, T., Sapatnekar, S.: Robust gate sizing by geometric programming. In: Proceedings of the ACM/IEEE design automation conference, Anaheim, pp. 315–320 (2005)Google Scholar
  21. 21.
    Srivastava, A., Sylvester, D., Blaauw, D.: Statistical optimization of leakage power consider process variations using dual-Vth and sizing. In: Proceedings of the ACM/IEEE design automation conference, San Diego, pp. 773–778 (2004)Google Scholar
  22. 22.
    Srivastava, A., Sylvester, D., Blaauw, D.: Power minimization using simultaneous gate sizing, dual Vdd and dual Vth assignment. In: Proceedings of the ACM/IEEE design automation conference, San Diego, pp. 783–787 (2004)Google Scholar
  23. 23.
    Abbas, Zia, Olivieri, Mauro, Yakupov, Marat, Ripp, Andreas: Design centering/yield optimization of power aware band pass filter based on CMOS current controlled Current Conveyor (CCCII+). Microelectron. J. 44(4), 321–331 (2013)CrossRefGoogle Scholar
  24. 24.
    Abbas, Z., Yakupov, M., Olivieri, M., Ripp, A., Strobe, G.: Yield optimization for low power current controlled current conveyor. In: Proceedings of 25th symposium on integrated circuits and systems design (SBCCI) (2012)Google Scholar
  25. 25.
    Abbas, Z., Khalid, U., Olivieri, M.: Sizing and optimization of low power process variation aware standard cells. In: IEEE international integrated reliability workshop final report (IIRW), pp. 181 (2013)Google Scholar
  26. 26.
    Mani, M., Devgan, A., Orshansky, M.: An efficient algorithm for statistical power under timing yield constraints. In: Proceedings of the ACM/IEEE design automation conference, Anaheim, pp. 309–314 (2005)Google Scholar
  27. 27.
    Davoodi, A., Srivastava, A.: Variability driven gate sizing for binning yield optimization. In: Proceedings of the ACM/IEEE design automation conference, San Francisco, pp. 956–964 (2006)Google Scholar
  28. 28.
    Singh, J., Sapatnekar, S.S.: A scalable statistical static timing analyzer incorporating correlated non-Gaussian and Gaussian parameter variations. IEEE Trans. Comput. Aided Des. Integr. Circuit Syst. 27(1), 160–173 (2008)CrossRefGoogle Scholar
  29. 29.
    HSPICE: MOS Reliability Analysis (MOSRA), Online:
  30. 30.
  31. 31.
    Abbas, Z., Mastrandrea, A., Olivieri, M.: A Voltage-based leakage current calculation scheme and its application to nanoscale MOSFET and FinFET standard-cell designs. IEEE Trans Very Large Scale Integr. (VLSI) Syst. 22(12), 2549–2560 (2014)CrossRefGoogle Scholar
  32. 32.
    Abbas, Z., Olivieri, M.: Impact of technology scaling on leakage power in nano-scale bulk CMOS digital standard cells. Microelectron. J. 45(2), 179–190 (2014)CrossRefGoogle Scholar
  33. 33.
    Sobe, U., Rooch, K.-H., Ripp, A., Pronath, M.: Robust analog design for automotive applications by design centering with safe operating areas. IEEE Trans. Semicond. Manuf. 22(2), 217–224 (2009)CrossRefGoogle Scholar
  34. 34.
    Antreich, K.J., Koblitz, R.K.: Design centering by yield optimization. IEEE Trans. Circuits Syst. 2, 43 (1982)Google Scholar
  35. 35.
    Antreich, K.J., Graeb, H.E.: Circuit optimization driven by worst-case distances. The Best of ICCAD—20 Years of Excellence in Computer—Aided Design, pp. 585–585. Kluwer Academic Publisher, Boston (2003)Google Scholar

Copyright information

© Springer Science+Business Media New York 2016

Authors and Affiliations

  1. 1.Department of Information Engineering, Electronics and TelecommunicationSapienza University of RomeRomeItaly
  2. 2.MunEDA GmbHMunichGermany

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