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Role of annealing temperature in the oxide charge distribution in high-\(\kappa \)-based MOS devices: simulation and experiment

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Abstract

The effect of rapid thermal annealing on the oxide charge distribution of Al/HfO\(_2\)/SiO\(_2\)/Si metal–oxide–semiconductor structures are studied using technology computer-aided design (TCAD) simulations and experiments. The simulated electrical characteristics are compared with experimentally obtained data. The interface traps are found to be nonuniform in nature and laterally distributed following a Gaussian profile. The distribution of interface trap charges arises because of spatial electric field variation in the oxide film upon gate bias application. The interface trap density is found to decrease with increase in annealing temperature. It is further observed that, at higher annealing temperature, the fixed oxide charge density increases due to interfacial Hf silicate formation.

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Acknowledgments

The authors would like to acknowledge Prof. Tapas Kumar Chini of Saha Institute of Nuclear Physics, Kolkata for providing the SEM facility. The authors would also like to thank the Department of Atomic Energy, Govt. of India for financial assistance.

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Author notes

  1. Ayan Chakraborty

    Present address: Indian Institute of Technology, Kharagpur, 721 302, India

Authors and Affiliations

  1. Saha Institute of Nuclear Physics, 1/AF, Bidhannagar, Kolkata, 700 064, India

    Debaleen Biswas & Supratic Chakraborty

  2. St. Thomas’ College of Engineering & Technology, 4, Diamond Harbour Road, Kolkata, 700 023, India

    Ayan Chakraborty

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  1. Debaleen Biswas
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Correspondence to Supratic Chakraborty.

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Biswas, D., Chakraborty, A. & Chakraborty, S. Role of annealing temperature in the oxide charge distribution in high-\(\kappa \)-based MOS devices: simulation and experiment. J Comput Electron 15, 795–800 (2016). https://doi.org/10.1007/s10825-016-0829-y

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