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Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs)

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Abstract

In this paper, an analytical model of the threshold voltage for short-channel symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs) is presented. The three-dimensional (3D) Poisson equation in cylindrical coordinates has been solved with suitable boundary conditions to find the surface potential along the channel length. The inversion charge density \((Q_{inv} )\) has been calculated in the channel region of the device in the subthreshold regime of device operation, using the Boltzmann relationship. Subsequently, the calculated inversion charge density \((Q_{inv} )\) has been equated to a threshold charge density \((Q_{th})\) in order to find the threshold voltage \((V_{th})\) expression. The effect of physical device parameters, including the tube thickness, on the threshold voltage and drain induced barrier lowering (DIBL) of the device has been discussed. The model results have been verified with the simulation data obtained by the device simulation software ATLAS.

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References

  1. Fahad, H.M., Hussain, M.M.: Are nanotube architectures more advantageous than nanowire architectures for field effect transistors? Sci. Rep. (2012). doi:10.1038/srep00475

  2. Tekleab, D.: Device performance of silicon nanotube field effect transistors. IEEE Electron Device Lett. 35, 506–508 (2014)

    Article  Google Scholar 

  3. Fahad, H.M., Smith, C.E., Rojas, J.P., Hussain, M.M.: Silicon nanotube field effect transistor with core-shell gate stacks for enhanced high-performance operation and area scaling benefits. Nano Lett. 11, 4393–4399 (2011)

    Article  Google Scholar 

  4. Tekleab, D., Tran, H.H., Slight, J.W., Chidambarrao, D.: Silicon nanotube MOSFET. Pub. No. US20120217468 A1 (2012)

  5. Kumar, M.J., Orouji, A.A., Dhakad, H.: New dual-material SG nanoscale MOSFET: analytical threshold-voltage model. IEEE Trans. Electron Devices 53, 920–923 (2006)

    Article  Google Scholar 

  6. Dubey, S., Santra, A., Saramekala, G.K., Kumar, M., Tiwari, P.K.: An analytical threshold voltage model for triple-material cylindrical gate-all-around (TM-CGAA) MOSFETs. IEEE Trans. Nanotechnol. 12, 766–773 (2013)

    Article  Google Scholar 

  7. Young, K.K.: Short-channel effect in fully depleted SO1 MOSFETs. IEEE Trans. Electron Devices 36, 399–402 (1989)

    Article  Google Scholar 

  8. Hamid, H.A.E., Iniguez, B., Guitart, J.R.: Analytical model of the threshold voltage and subthreshold swing of undoped cylindrical gate-all-around-based MOSFETs. IEEE Trans. Electron Devices 54, 572–579 (2007)

    Article  Google Scholar 

  9. Tiwari, P.K., Dubey, S., Singh, M., Jit, S.: A two-dimensional analytical model for threshold voltage of short-channel triple-material double-gate metal-oxide-semiconductor field-effect transistors. J. Appl. Phys. 108, 074508 (2010)

    Article  Google Scholar 

  10. Chen, Q., Harrell II, E.M., Meindl, J.D.: A physical short-channel threshold voltage model for undoped symmetric double-gateMOSFETs. IEEE Trans. Electron Devices 50, 1631–1637 (2003)

    Article  Google Scholar 

  11. Omura, Y., Horiguchi, S., Tabe, M., Kishi, K.: Quantum-mechanical effects on the threshold voltage of ultrathin-SOI NMOSFETs. IEEE Electron Device Lett. 14, 569–571 (1993)

    Article  Google Scholar 

  12. ATLAS User’s Manual: Device Simulation Software. SilvacoInternational, Santa Clara (2008)

    Google Scholar 

  13. Tsormpatzoglou, A., Dimitriadis, C.A., Clerc, R., Pananakakis, G., Ghibaudo, G.: Threshold voltage model for short-channel undoped symmetrical double-gate MOSFETs. IEEE Trans. Electron Devices 55, 2512–2516 (2008)

    Article  Google Scholar 

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Acknowledgments

One of the authors, Dr. P. K. Tiwari, acknowledges the financial support received from Defence Research and Development Organisation (DRDO), Ministry of Defence, Government of India (Grant No. CC/TM/ERIPR/GIA/1516/020).

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Correspondence to Pramod Kumar Tiwari.

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Tiwari, P.K., Samoju, V.R., Sunkara, T. et al. Analytical modeling of threshold voltage for symmetrical silicon nano-tube field-effect-transistors (Si-NT FETs). J Comput Electron 15, 516–524 (2016). https://doi.org/10.1007/s10825-016-0819-0

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