Journal of Computational Electronics

, Volume 13, Issue 2, pp 400–407 | Cite as

Improvement of electrical characteristics of local BOX MOSFETs by heavily doped structures and elucidation of the related mechanism

  • Tatsuya Yamada
  • Yoshikata Nakajima
  • Tatsuro Hanajiri
  • Toru Toyabe
  • Takuo Sugano
Article
  • 130 Downloads

Abstract

We proposed heavily doped silicon between insulators (HDSBI) MOSFETs to improve electrical characteristics of local BOX MOSFETs by using simple structures that combine local BOX regions with additional doped regions. HDSBI MOSFETs have heavily doped regions between local BOX regions, in which acceptors or traps are introduced. Simulated electrical characteristics demonstrated that they can suppress the SCEs and the kink effect, as well as the self-heating effect (SHE), which is suppressed by conventional local BOX MOSFETs. We elucidated how the additional doped regions in HDSBI MOSFETs suppress the SCEs and the kink effect. We concluded that HDSBI MOSFETs are suitable for applications, such as multi-purpose system-on-chip on which both short-channel logic circuits and high drive current circuits are integrated.

Keywords

Silicon-on-insulator (SOI) Ground plane Trap states Buried-oxide (BOX) layer Device simulation Kink effect Body floating effect Short-channel effect (SCE) 

Notes

Acknowledgements

This work is supported by VLSI Design and Education Center (VDEC), the University of Tokyo in collaboration with Synopsys, Inc. The part of the device simulations has been supported by Y. Miyazawa.

References

  1. 1.
    Colinge, J.-P.: Silicon-on-Insulator Technology: Materials to VLSI. Kluwer, Boston (2004) CrossRefGoogle Scholar
  2. 2.
    Kleiner, M.B., Kuhn, S.A., Weber, W.: Thermal conductivity measurements of thin silicon dioxide films in integrated circuits. IEEE Trans. Electron Devices 43, 1602–1609 (1996) CrossRefGoogle Scholar
  3. 3.
    Choi, J.-Y., Fossum, J.G.: Analysis and control of floating-body bipolar effects in fully depleted submicrometer SOI MOSFET’s. IEEE Trans. Electron Devices 38, 1384–1391 (1991) CrossRefGoogle Scholar
  4. 4.
    Koh, R.: Buried layer engineering to reduce the drain-induced barrier lowering of sub-0.05 μm SOI-MOSFET. Jpn. J. Appl. Phys. 38, 2294–2299 (1999) CrossRefGoogle Scholar
  5. 5.
    Monfray, S., Skotnicki, T., Fenouillet-Beranger, C., Carriere, N., Chanemougame, D., Morand, Y., Descombes, S., Talbot, A., Dutartre, D., Jenny, C., Mazoyer, P., Palla, R., Leverd, F., Le Friec, Y., Pantel, R., Borel, S., Louis, D., Buffet, N.: Emerging silicon-on-nothing (SON) devices technology. Solid-State Electron. 48, 887–895 (2004) CrossRefGoogle Scholar
  6. 6.
    Yamada, T., Nakajima, Y., Hanajiri, T., Sugano, T.: Suppression of drain-induced barrier lowering in silicon-on-insulator MOSFETs through source/drain engineering for low-operating-power system-on-chip applications. IEEE Trans. Electron Devices 60, 260–267 (2013) CrossRefGoogle Scholar
  7. 7.
    Yamada, T., Abe, S., Nakajima, Y., Hanajiri, T., Toyabe, T., Sugano, T.: Quantitative extraction of electric flux in the buried-oxide layer and investigation of its effects on MOSFET characteristics. IEEE Trans. Electron Devices 60, 3996–4001 (2013) CrossRefGoogle Scholar
  8. 8.
    He, P., Jiang, B., Lin, X., Liu, L., Tian, L., Li, Z., Dong, Y., Chen, M., Wang, X.: Experimental results on drain and source on insulator MOSFETs fabricated by local SIMOX technology. Solid-State Electron. 47, 1061–1067 (2003) CrossRefGoogle Scholar
  9. 9.
    Dong, Y., Chen, M., Chen, J., Wang, X., Wang, X., He, P., Lin, X., Tian, L., Li, Z.: Patterned buried oxide layers under a single MOSFET to improve the device performance. Semicond. Sci. Technol. 19, L25–L28 (2004) CrossRefGoogle Scholar
  10. 10.
    Tian, Y., Huang, R., Zhang, X., Wang, Y.: A novel nanoscaled device concept: quasi-SOI MOSFET to eliminate the potential weaknesses of UTB SOI MOSFET. IEEE Trans. Electron Devices 52, 561–568 (2005) CrossRefGoogle Scholar
  11. 11.
    Tian, Y., Xiao, H., Huang, R., Feng, C., Chan, M., Chen, B., Wang, R., Zhang, X., Wang, Y.: Quasi-SOI MOSFETs—a promising bulk device candidate for extremely scaled era. IEEE Trans. Electron Devices 54, 1784–1788 (2007) CrossRefGoogle Scholar
  12. 12.
    Xiao, H., Huang, R., Liang, J., Liu, H., Tian, Y., Wang, R., Wang, Y.: The localized-SOI MOSFET as a candidate for analog/RF applications. IEEE Trans. Electron Devices 54, 1978–1984 (2007) CrossRefGoogle Scholar
  13. 13.
    Lin, J.-T., Eng, Y.-C.: Influence of block oxide width on a silicon-on-partial-insulator field-effect transistor. IEEE Trans. Electron Devices 54, 2893–2900 (2007) CrossRefGoogle Scholar
  14. 14.
    Wong, H.-S.P., Frank, D.J., Solomon, P.M.: Device design considerations for double-gate, ground-plane, and single-gated ultra-thin SOI MOSFET’s at the 25 nm channel length generation. In: International Electron Devices Meeting 1998. Technical Digest (Cat. No. 98CH36217), pp. 407–410. IEEE, New York (1998) CrossRefGoogle Scholar
  15. 15.
    Narasimhulu, K., Sharma, D.K., Rao, V.R.: Impact of lateral asymmetric channel doping on deep submicrometer mixed-signal device and circuit performance. IEEE Trans. Electron Devices 50, 2481–2489 (2003) CrossRefGoogle Scholar
  16. 16.
    Hu, G., Dennard, R.H., Terman, L.M., Petrillo, K.E.: A self-aligned 1-µ m-channel CMOS technology with retrograde n-well and thin epitaxy. IEEE Trans. Electron Devices 32, 203–209 (1985) CrossRefGoogle Scholar
  17. 17.
    Ogura, S., Tsang, P.J., Walker, W.W., Critchlow, D.L., Shepard, J.F.: Design and characteristics of the lightly doped drain-source (LDD) insulated gate field-effect transistor. IEEE Trans. Electron Devices 27, 1359–1367 (1980) CrossRefGoogle Scholar
  18. 18.
  19. 19.
    Wachutka, G.: An extended thermodynamic model for the simultaneous simulation of the thermal and electrical behavior of semiconductor devices. In: Proceedings of the Sixth International Conference on the Numerical Analysis of Semiconductor Devices and Integrated Circuits (NASECODE VI), Dublin, Ireland, pp. 409–414 (1989) Google Scholar
  20. 20.
    Ancona, M., Iafrate, G.: Quantum correction to the equation of state of an electron gas in a semiconductor. Phys. Rev. B 39, 9536–9540 (1989) CrossRefGoogle Scholar
  21. 21.
    Paasch, G., Übensee, H.: A modified local density approximation. electron density in inversion layers. Phys. Status Solidi 113, 165–178 (1982) CrossRefGoogle Scholar
  22. 22.
    Schenk, A.: Rigorous theory and simplified model of the band-to-band tunneling in silicon. Solid-State Electron. 36, 19–34 (1993) CrossRefGoogle Scholar
  23. 23.
    Van Overstraeten, R., De Man, H.: Measurement of the ionization rates in diffused silicon p–n junctions. Solid-State Electron. 13, 583–608 (1970) CrossRefGoogle Scholar
  24. 24.
    Kim, S.-D.: Optimum location of silicide/Si interface in ultra-thin body SOI MOSFETs with recessed and elevated silicide source/drain contact structure. Solid-State Electron. 53, 1112–1115 (2009) CrossRefGoogle Scholar
  25. 25.
    Brammer, T., Stiebig, H.: Defect density and recombination lifetime in microcrystalline silicon absorbers of highly efficient thin-film solar cells determined by numerical device simulations. J. Appl. Phys. 94, 1035 (2003) CrossRefGoogle Scholar
  26. 26.
    Hack, M., Shur, M.: Analysis of light-induced degradation in amorphous silicon alloy p–i–n solar cells. J. Appl. Phys. 58, 1656 (1985) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media New York 2013

Authors and Affiliations

  • Tatsuya Yamada
    • 1
  • Yoshikata Nakajima
    • 1
  • Tatsuro Hanajiri
    • 1
  • Toru Toyabe
    • 1
  • Takuo Sugano
    • 1
  1. 1.Bio-Nano Electronics Research CentreToyo UniversitySaitamaJapan

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