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Impact of series resistance on Si nanowire MOSFET performance

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Abstract

In gate all around (GAA) nanowire (NW) MOSFETs large series resistance due to narrow width extension regions is an important issue, playing a critical role in determining device and circuit performance. In this paper, we present a series resistance model and analyze its dependence on geometry/process parameters. The series resistance is modelled by dividing it into five resistance components namely spreading resistance, extension resistance, interface resistance, deep source-drain resistance and contact resistance. The model is validated using 3-D device simulations of 22 nm GAA devices with Source/Drain extension (SDE) length of 15 nm to 35 nm, diameter of 8 nm to 16 nm and oxide thickness of 10 A to 40 A for both n-FET and p-FET. It is found that the spreading resistance due to lateral doping gradient contributes significantly to the total series resistance. Further, the dependence of NW device performance on series resistance is quantitatively investigated with change of diameter, SDE length and Source/Drain (S/D) implantation dose. Results show a strong NW device performance dependence on S/D doping profile and extension length defining a design trade-off between Short Channel Effects (SCEs) and series resistance. It is seen that the increase in series resistance due to increase of extension length or decrease of implantation dose beyond a certain limit reduces the device drive current significantly with nearly constant OFF-state leakage current. Hence, optimization of extension length and S/D implant dose is an important device design issue for sub 22 nm technology nodes.

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References

  1. Bangsaruntip, S., Cohen, G.M., Majumdar, A., Zhang, Y., Engelmann, S.U., Fuller, N.C.M., Gignac, L.M.: High performance and highly uniform gate-all-around silicon nanowire MOSFETs with wire size dependent scaling. In: IEDM Tech. Dig., pp. 1–4 (2009)

    Google Scholar 

  2. Kim, J., Yang, S., Lee, J., Suk, S.D., Seo, K., Park, D., Park, B.-G., Lee, J.D., Shin, H.: Investigation of mobility in twin silicon nanowire MOSFETs (TSNWFETs). In: ICSICT, pp. 50–52 (2008)

    Google Scholar 

  3. Singh, N., Lim, F.Y., Fang, W.W., Rustagi, S.C., Bera, L.K., Agarwal, A., Tung, C.H.: Ultra-narrow silicon nanowire gate-all-around CMOS devices: impact of diameter, channel-orientation and low temperature on device performance. In: IEDM Tech. Dig., pp. 1–4 (2006)

    Google Scholar 

  4. Choi, L., Hak Hong, B., Jung, Y.C., Cho, K.H., Yeo, K.H., Kim, D.-W., Jin, G.Y., Oh, K.S., Lee, W.-S., Song, S.-H., Rieh, J.S., Whang, D.M., Hwang, S.W., et al.: Extracting mobility degradation and total series resistance of cylindrical gate-all-around silicon nanowire field-effect transistors. IEEE Trans. Electron Devices Lett. 30(6), 665–667 (2009)

    Article  Google Scholar 

  5. Baek, R.-H., Baek, C.-K., Jung, S.-W., Yeoh, Y.Y., Kim, D.-W., Lee, J.-S., Kim, D., Jeong, Y.-H.: Characteristics of the series resistance extracted from si nanowire FETs using the Y-function technique. IEEE Trans. Nanotechnol. 9(2), 212–217 (2010)

    Article  Google Scholar 

  6. Han, J.-W., Moon, D.-I., Choi, Y.-K.: High aspect ratio silicon nanowire for stiction immune gate-all-around MOSFETs. IEEE Trans. Electron Devices Lett. 30(8), 864–866 (2009)

    Article  Google Scholar 

  7. Liu, M., Cai, M., Yu, B., Taur, Y.: Effect of gate overlap and source/drain doping gradient on 10-nm CMOS performance. IEEE Trans. Electron Devices 53(12), 3146–3149 (2006)

    Article  Google Scholar 

  8. Shenoy, R.S., Saraswat, C.: Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs. IEEE Trans. Nanotechnol. 2(6), 265–270 (2003)

    Article  Google Scholar 

  9. Trivedi, V., Fossum, J.G., Chowdhury, M.M.: Nanoscale FinFETs with gate-source/drain underlap. IEEE Trans. Electron Devices 52(1), 56–62 (2005)

    Article  Google Scholar 

  10. Sentaurus TCAD: (ver. G-2012.06) Manuals Synopsis Inc.

  11. Wettstein, A., Schenk, A., Fichtner, W.: Quantum device-simulation with the density-gradient model on unstructured grids. IEEE Trans. Electron Devices 48(2), 279–284 (2001)

    Article  Google Scholar 

  12. Lyudis, E., Mickevicius, R., Penzin, O., Polsky, B., El Sayed, K., Wettstein, A., Fichtner, W.: Density gradient transport model for the simulations of ultrathin, ultrashort SOI under non-equilibrium conditions. In: SOI Conference, pp. 143–144 (2002)

    Google Scholar 

  13. Mamaluy, D., Vasileska, D., Sabathil, M., Zibold, T., Vogl, P.: Contact block reduction method for ballistic transport and carrier densities of open nanostructures. Phys. Rev. B 71, 245321 (2005)

    Article  Google Scholar 

  14. Khan, H.R., Mamaluy, D., Vasileska, D.: Quantum transport simulation of experimentally fabricated nano-FinFET. IEEE Trans. Electron Devices 54(4), 784–796 (2007)

    Article  Google Scholar 

  15. Bude, J.D.: MOSFET modeling into the ballistic regime. In: SISPAD, pp. 23–26 (2000)

    Google Scholar 

  16. Allen, L.H., Zhang, M.Y., Mayer, J.W., Colgan, E.G., Young, R.: Solutions to current crowding in circular vias for contact resistance measurements. J. Appl. Phys. Jul., 253–258 (1991)

    Article  Google Scholar 

  17. Trivedi, V.P., Fossum, J.G.: Quantum-mechanical effects on the threshold voltage of undoped double-gate MOSFETs. IEEE Electron Device Lett. 26(8), 579–582 (2005)

    Article  Google Scholar 

  18. Suk, S.D., Li, M., Yeoh, Y.Y., Yeo, K.H., Cho, K.H., Ku, I.K., Cho, H., Jang, W.J., Kim, D.-W., Park, D., Lee, W.-S.: Investigation of nanowire size dependency on TSNWFET. In: IEDM, pp. 891–894 (2007)

    Google Scholar 

  19. Kim, S.-D., Park, C.-M., Woo, J.C.S.: Advanced model and analysis of series resistance for CMOS scaling into nanometer regime—Part I: theoretical derivation. IEEE Trans. Electron Devices 49(3), 457–466 (2002)

    Article  Google Scholar 

  20. Taur, Y.: MOSFET channel length: extraction and interpretation. IEEE Trans. Electron Devices 47(1), 160–170 (2000)

    Article  Google Scholar 

  21. Dixit, A., Kottantharayil, A., Collaert, N., Goodwin, M., Jurczak, M., De Meyer, K.: Analysis of the parasitic S/D resistance in multiple-gate FETs. IEEE Trans. Electron Devices 52(6), 1132–1140 (2005)

    Article  Google Scholar 

  22. Jiang, Y., Liow, T.Y., Singh, N., Tan, L.H., Lo, G.Q., Chan, D.S.H., Kwong, D.L.: Performance breakthrough in 8 nm gate length gate-all-around nanowire transistors using metallic nanowire contacts. In: VLSI Tech, pp. 34–35 (2008)

    Google Scholar 

  23. Mudanai, S., Chindalore, G.L., Shih, W.-K., Wang, H., Ouyang, Q., Tasch, A.F., Maziar, C.M., Banerjee, S.K.: Models for electron and hole mobilities in MOS accumulation layers. IEEE Trans. Electron Devices 46, 1749–1759 (1999)

    Article  Google Scholar 

  24. Ke, W., Han, X., Xu, B., Liu, X., Wang, X., Zhang, T., Han, R., Zhang, S.: Source/drain series resistances of nanoscale ultra-thin-body SOI MOSFETs with undoped or very-low-doped channel regions. Semicond. Sci. Technol. 21, 1416–1421 (2006)

    Article  Google Scholar 

  25. Shenoy, R.S., Saraswat, C.: Optimization of extrinsic source/drain resistance in ultrathin body double-gate FETs. IEEE Trans. Nanotechnol. 2(6), 265–270 (2003)

    Article  Google Scholar 

  26. Khan, H.R., Mamaluy, D., Vasileska, D.: Simulation of the impact of process variation on the optimized 10-nm FinFET. IEEE Trans. Electron Devices 55(8), 2134–2141 (2008)

    Article  Google Scholar 

  27. Song, Y., Xu, Q., Luo, J., Zhou, H., Niu, J., Liang, Q., Zhao, C.: Performance breakthrough in gate-all-around nanowire n- and p-type MOSFETs fabricated on bulk silicon substrate. IEEE Trans. Electron Devices 59(7), 1885–1890 (2012)

    Article  Google Scholar 

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Authors and Affiliations

  1. Microelectronics and VLSI, Dept. of Electronics and Computer Engineering, Indian Institute of Technology, Roorkee, 247667, India

    G. Kaushal, S. K. Manhas, S. Maheshwaram & S. Dasgupta

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  1. G. Kaushal
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  2. S. K. Manhas
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  3. S. Maheshwaram
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  4. S. Dasgupta
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Correspondence to G. Kaushal or S. K. Manhas.

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Kaushal, G., Manhas, S.K., Maheshwaram, S. et al. Impact of series resistance on Si nanowire MOSFET performance. J Comput Electron 12, 306–315 (2013). https://doi.org/10.1007/s10825-013-0449-8

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  • DOI: https://doi.org/10.1007/s10825-013-0449-8

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