Journal of Computational Electronics

, Volume 11, Issue 4, pp 303–314 | Cite as

Semi-analytical modeling of Ag and Au nanoparticles and fullerene (C60) embedded gate oxide compound semiconductor MOSFET memory devices

  • Amretashis Sengupta
  • Chandan Kumar Sarkar
  • Felix G. Requejo
Article

Abstract

In this paper we present an analytical simulation study of Non-volatile MOSFET memory devices with Ag/Au nanoparticles/fullerene (C60) embedded gate dielectric stacks. We considered a long channel planar MOSFET, having a multilayer SiO2–HfO2 (7.5 nm)–Ag/Au nc/C60 embedded HfO2 (6 nm)–HfO2 (30 nm) gate dielectric stack. We considered three substrate materials GaN, InP and the conventional Si substrate, for use in such MOSFET NVM devices. From a semi-analytic solution of the Poisson equation, the potential and the electric fields in the substrate and the different layers of the gate oxide stack were derived. Thereafter using the WKB approximation, we have investigated the Fowler-Nordheim tunneling currents from the Si inversion layer to the embedded nanocrystal states in such devices. From our model, we simulated the write-erase characteristics, gate tunneling currents, and the transient threshold voltage shifts of the MOSFET NVM devices. The results from our model were compared with recent experimental results for Au nc and Ag nc embedded gate dielectric MOSFET memories. From the studies, the C60 embedded devices showed faster charging performance and higher charge storage, than both the metallic nc embedded devices. The nc Au embedded device displayed superior characteristics compared to the nc Ag embedded device. From the model GaN emerged as the overall better substrate material than Si and InP in terms of higher threshold voltage shift, lesser write programming voltage and better charge retention capabilities.

Keywords

Long channel MOSFET Non-volatile memory C60 Ag nanocrystal Au nanocrystal 

References

  1. 1.
    Tiwari, S., Rana, F., Hanafi, H., Hartstein, A., Crabbe, E.F., Chan, K.: A silicon nanocrystals based memory. Appl. Phys. Lett. 68, 1377 (1996) CrossRefGoogle Scholar
  2. 2.
    Ng, C.Y., Chen, T.P., Zhao, P., Ding, L., Liu, Y., Tseng, A.A., Fung, S.: Electrical characteristics of Si nanocrystal distributed in a narrow layer in the gate oxide near the gate synthesized with very-low-energy ion beams. J. Appl. Phys. 99, 106105 (2006) CrossRefGoogle Scholar
  3. 3.
    Yang, M., Chen, T.P., Wong, J.I., Liu, Y., Tseng, A.A., Fung, S.: Charge storage behaviors of Ge nanocrystals embedded in SiO2 for the application in non-volatile memory devices. J. Nanosci. Nanotechnol. 10, 4517 (2010) CrossRefGoogle Scholar
  4. 4.
    Guan, W., Long, S., Liu, M., Li, Z., Hu, Y., Liu, Q.: Fabrication and charging characteristics of MOS capacitor structure with metal nanocrystals embedded in gate oxide. J. Phys. D, Appl. Phys. 40, 2754 (2007) CrossRefGoogle Scholar
  5. 5.
    Mikhelashvili, V., Meyler, B., Yofis, S., Shneider, Y., Zeidler, A., Garbrecht, M., Cohen-Hyams, T., Kaplan, W.D., Lisiansky, M., Roizin, Y., Salzman, J., Einstein, G.: Nonvolatile low-voltage memory transistors based on SiO2 tunneling and HfO2 blocking layers with charge storage in Au nanocrystals. Appl. Phys. Lett. 98, 212902 (2011) CrossRefGoogle Scholar
  6. 6.
    Ryu, S.-W., Mo, C.B., Hong, S.H., Choi, Y.-K.: Nonvolatile memory characteristics of NMOSFET with Ag nanocrystals synthesized via a thermal decomposition process for uniform device distribution. IEEE Trans. Nanotechnol. 7, 145 (2008) CrossRefGoogle Scholar
  7. 7.
    Lu, X.B., Dai, J.Y.: Memory effects of carbon nanotubes as charge storage nodes for floating gate memory applications. Appl. Phys. Lett. 88, 113104 (2006) CrossRefGoogle Scholar
  8. 8.
    Kim, S.H., Yokoyama, M., Taoka, N., Iida, R., Lee, S., Nakane, R., Urabe, Y., Miyata, N., Yasuda, T., Yamada, H., Fukuhara, N., Hata, M., Takenaka, M., Takagi, S.: Self-aligned metal source/drain InP n-metal-oxide-semiconductor field-effect transistors using Ni–InP metallic alloy. Appl. Phys. Lett. 98, 243501 (2011) CrossRefGoogle Scholar
  9. 9.
    Lee, H.-B., Cho, H.-I., An, H.-S., Bae, Y.-H., Lee, M.-B., Lee, J.-H., Hahm, S.-H.: A normally off GaN n-MOSFET with Schottky-barrier source and drain on a Si-auto-doped p-GaN/Si. IEEE Electron Device Lett. 27, 81 (2006) CrossRefGoogle Scholar
  10. 10.
    Im, K.-S., Ha, J.-B., Kim, K.-W., Lee, J.-S., Kim, D.-S., Hahm, S.-H., Lee, J.-H.: Normally off GaN MOSFET based on AlGaN/GaN heterostructure with extremely high 2DEG density grown on silicon substrate. IEEE Electron Device Lett. 31, 192 (2010) CrossRefGoogle Scholar
  11. 11.
    Longo, P., Jansen, W., Merckling, C., Penaud, J., Caymax, M., Thayne, I.G., Craven, A.J.: Electron Microscopy and Analysis Group Conference 2009 (EMAG 2009). J. Phys. Conf. Ser. 241, 012037 (2010) CrossRefGoogle Scholar
  12. 12.
    Cha, H.-Y., Wu, H., Chae, S., Spencer, M.G.: Gallium nitride nanowire nonvolatile memory device. J. Appl. Phys. 100, 024307 (2006) CrossRefGoogle Scholar
  13. 13.
    Hao, L.Z., Zhu, J., Luo, W.B., Zeng, H.Z., Li, Y.R., Zhang, Y.: Electron trap memory characteristics of LiNbO3 film/AlGaN/GaN heterostructure. Appl. Phys. Lett. 96, 032103 (2010) CrossRefGoogle Scholar
  14. 14.
    Chang, L.B., Das, A., Lin, R.M., Maikap, S., Jeng, M.J., Chou, S.T.: An observation of charge trapping phenomena in GaN/AlGaN/Gd2O3/Ni–Au structure. Appl. Phys. Lett. 98, 222106 (2011) CrossRefGoogle Scholar
  15. 15.
    Das, A., Be Chang, L., Lin, R.M., Maikap, S.: An observation of charge trapping phenomena in GaN/AlGaN/Gd2O3MOS Schottky structure. In: Proc. 4th IEEE International NanoElectronics Conference (INEC-2011), Taiwan, 1–2 June 2011 Google Scholar
  16. 16.
    Abebe, H., Cumberbatch, E., Tyree, V., Morris, H.: In: Proceedings 2005 Nanotechnology Conference, Anaheim, CA, May 8–12, vol. 3, pp. 64–67 (2005) Google Scholar
  17. 17.
    van Langevelde, R., Klaassen, F.M.: An explicit surface-potential-based MOSFET model for circuit simulation. Solid-State Electron. 44, 409 (2000) CrossRefGoogle Scholar
  18. 18.
    Chen, T.L., Gildenblat, G.: Analytical approximation for the MOSFET surface potential. Solid-State Electron. 45, 335 (2001) CrossRefGoogle Scholar
  19. 19.
    Sengupta, A., Sarkar, C.K., Requejo, F.G.: Comparative study of CNT, silicon nanowire and fullerene embedded multilayer high-k gate dielectric MOS memory devices. J. Phys. D, Appl. Phys. 44, 405101 (2011) CrossRefGoogle Scholar
  20. 20.
    De Salvo, B., Ghibuado, G., Pananakakis, G., Masson, P., Baron, T., Buffet, N., Fernandes, A., Guillaumot, B.: Experimental and theoretical investigation of nano-crystal and nitride-trap memory devices. IEEE Trans. Electron Devices 48, 1789 (2001) CrossRefGoogle Scholar
  21. 21.
    Lambert, R.H.: Density of states in a sphere and cylinder. Am. J. Phys. 36, 417–420 (1968) CrossRefGoogle Scholar
  22. 22.
    Amoroso, S.M., Compagnoni, C.M., Mauri, A., Maconi, A., Spinelli, A.S., Lacaita, A.L.: Semi-analytical model for the transient operation of gate-all-around charge-trap memories. IEEE Trans. Electron Devices 58, 3116 (2011) CrossRefGoogle Scholar
  23. 23.
    Sengupta, A., Shah, P., Sarkar, C.K., Requejo, F.G.: Computational study on semiconducting and metallic nanocrystal embedded gate oxide MOS non volatile memory devices. Adv. Sci. Lett. 10, 47 (2012) CrossRefGoogle Scholar

Copyright information

© Springer Science+Business Media LLC 2012

Authors and Affiliations

  • Amretashis Sengupta
    • 1
    • 3
  • Chandan Kumar Sarkar
    • 1
  • Felix G. Requejo
    • 2
  1. 1.Department of Electronics & Telecommunication EngineeringJadavpur UniversityKolkataIndia
  2. 2.INIFTA, Departmento de Quimica & Departmento de Fisica, Facultad de Ciencias ExactasUniversidad Nacional de La PlataLa PlataArgentina
  3. 3.NanoScale Device Research Laboratory, Department of Electronic Systems Engineering (formerly CEDT)Indian Institute of Science (IISc)BangaloreIndia

Personalised recommendations