Skip to main content
Log in

Forbidden pitches in sub-wavelength lithography and their implications on design

  • Published:
Journal of Computer-Aided Materials Design

Abstract

Moore’s Law has been the most important benchmark for microelectronics development over the past four decades. It has been interpreted to mean that critical dimensions (CD) of a design must shrink geometrically over time. The chip-level integration of devices has been possible through concurrent improvement in lithographic resolution. The lithographic resolution was primarily improved by moving deeper into ultraviolet spectrum of light. However, the wavelength of the optical source used for lithography has not improved for nearly a decade. This has lead to the development of sub-wavelength lithography. The diffraction effects of sub-wavelength lithography were offset by optical proximity correction (OPC), phase shift masking (PSM) and impending move to immersion lithography. Unfortunately, one time benefits from each of these resolution enhancement techniques (RET) have nearly exhausted. In this paper, we explore one important diffraction aspect of sub-wavelength lithography viz. the forbidden pitch phenomenon and its implication on future designs. We studied Forbidden pitches in context of 65 and 45 nm technologies using aerial imaging simulation. Aerial imaging simulation is computationally expensive and is not possible to perform on entire layout structures. Based on results from our simulations on selected patterns, we observe that in absence of any other resolution enhancement technique, many of the current layout patterns will be disallowed in 45 nm technology. Such restrictions significantly mitigate the benefit of migration to 45 nm technology in terms of area, power and performance of a design. We further show that even structured gate array based designs are not immune to this problem.

This is a preview of subscription content, log in via an institution to check access.

Access this article

Price excludes VAT (USA)
Tax calculation will be finalised during checkout.

Instant access to the full article PDF.

Similar content being viewed by others

References

  1. Moore G.E. (1965) Cramming more components onto integrated circuits. Electron. 38, 114–117

    Google Scholar 

  2. Information available at: http://www.hpcwire.com/

  3. Chau, R., Doyle, B., Doczy, M., Datta, S., Hareland, S., Jin, B., Kavalieros, J., Metz, M.: Silicon Nano-Transistors and Breaking the 10 nm Physical Gate Length Barrier. Intel Research Technical Report IR-TR-2003–7 (2003)

  4. Schellenberg, F.: A Little light magic, IEEE Spect. 40 34–39

  5. Lord Rayleigh (1872) On the diffraction of object glasses. Mon. Not. R. Astron. Soc. 33, 59–63

    Google Scholar 

  6. Mack, C.A.: Understanding focus effects in submicron optical lithography. In: Optical/Laser Microlithography, Proceedings of the SPIE 922, 135–148 (1988); Opt. Eng. 27(12), 1093–1100 (1988)

  7. Hopkins H.H. (1953) On the diffraction theory of optical images. Proc. R. Soc. Lond. A Math. Phys. Sci. 217(1130): 408–432

    Article  Google Scholar 

  8. Wong, A.K. et al.: Forbidden area avoidance with spacing technique for layout optimization. In: Proceedings of SPIE, vol. 5379, pp. 67–75 (2004)

  9. Shi, X., Hsu, S., Chen, F., Hsu, M., Socha, R., Dusa, M.: Understanding the Forbidden Pitch Phenomenon and Assist Feature Placement. In: Microlithography XVI, Proceedings of the SPIE vol. 4689 (2000)

  10. Socha, R., Dusa, M., Capodieci, L., Finders, J., Chen, F., Flagello, D., Cummings, K.: Forbidden pitches for 130 nm lithograph and below. Optical Microlithography XIII, In: Progler, C.J. (ed). Proceedings of SPIE, vol. 4000, pp. 1140–1155 (2000)

  11. James, D.: 2004—The Year of 90-nm: A Review of 90 nm Devices. In: Proceedings of the IEEE Advanced Semiconductor Manufacturing Conference, pp. 72–76 (2005)

  12. Brglez, F., Fujiwara, H.: A neutral netlist of 10 combinational benchmark circuits and a target translator in fortran. Proc. IEEE Int. Symp. Circuits Sys. 663–698, pp. 671–674 (1985)

  13. Pileggi, L., Schmit, H., Strojwas, A.J., Gopalakrishanan, P., Kheterpal, V., Koorapaty, A., Patel, C., Rovner, V., Tong, K.Y.: Exploring regular fabrics to optimize the performance-cost trade-off. Proc. DAC, 782–787 (2003)

  14. Tong, K.Y., Kheterapal, V., Rovner, S., Schmit, H., Pileggi, L., Puri, R.: Regular logic fabrics for a Via patterned gate array (VPGA). In: Proceedings of the Int’l Custom Integrated Circuits Conference, pp. 53–56 (2003)

Download references

Author information

Authors and Affiliations

Authors

Corresponding author

Correspondence to Sandip Kundu.

Rights and permissions

Reprints and permissions

About this article

Cite this article

Kundu, S., Sreedhar, A. & Sanyal, A. Forbidden pitches in sub-wavelength lithography and their implications on design. J Computer-Aided Mater Des 14, 79–89 (2007). https://doi.org/10.1007/s10820-006-9044-7

Download citation

  • Received:

  • Accepted:

  • Published:

  • Issue Date:

  • DOI: https://doi.org/10.1007/s10820-006-9044-7

Keywords

Navigation