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Adaptive Multimodule Routers for Multiprocessor Architectures

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Abstract

Recent multiprocessors such as Cray T3D support interprocessor communication using partitioned dimension-order routers (PDRs). In a PDR implementation, the routing logic and switching hardware is partitioned into multiple modules, with each module suitable for implementation as a chip. This paper proposes a method to incorporate adaptivity into such routers with simple changes to the router structure and logic. We show that with as few as two virtual channels per physical channel, adaptivity can be provided to handle nonuniform traffic in multidimensional meshes.

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Authors and Affiliations

  1. School of Business and Technology, University of Wisconsin-Parkside, Kenosha, WI, 53141

    Suresh Chalasani

  2. Computer Science Department, The Univ. of Texas at San Antonio, San Antonio, TX, 78249

    Rajendra V. Boppana

Authors
  1. Suresh Chalasani
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  2. Rajendra V. Boppana
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Correspondence to Suresh Chalasani.

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Chalasani, S., Boppana, R.V. Adaptive Multimodule Routers for Multiprocessor Architectures. Inf Syst Front 7, 317–327 (2005). https://doi.org/10.1007/s10796-005-2772-5

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  • DOI: https://doi.org/10.1007/s10796-005-2772-5

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