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New Design of Reversible Full Adder/Subtractor Using R Gate

Abstract

Quantum computers require quantum processors. An important part of the processor of any computer is the arithmetic unit, which performs binary addition, subtraction, division and multiplication, however multiplication can be performed using repeated addition, while division can be performed using repeated subtraction. In this paper we present two designs using the reversible R3 gate to perform the quantum half adder/subtractor and the quantum full adder/subtractor. The proposed half adder/subtractor design can be used to perform different logical operations, such as AND, XOR, NAND, XNOR, NOT and copy of basis. The proposed design is compared with the other previous designs in terms of the number of gates used, the number of constant bits, the garbage bits, the quantum cost and the delay. The proposed designs are implemented and tested using GAP software.

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References

  1. 1.

    Ni, L., Guan, Z., Zhu, W.: A general method of constructing the reversible full-adder. Third Internatinal Symposium on Information Technology and Security Informatics. IEEE, 109–113 (2010)

  2. 2.

    Babu, H., Islam, M., Chowdhury, A., Chowdhury, S.: Reversible logic synthesis for minimization of full-adder circuit. The Euromicro Symposium on Digital System Design. IEEE, 1–5 (2003)

  3. 3.

    Khlopotine, A., Perkowski, M., Kerntopf, P.: Reversible logic synthesis by iterative compositions. IWLS, 1–5 (2002)

  4. 4.

    Islam, S., Islam, R.: Minimization of reversible adder circuits. Asian Journal of Information Technology. Medwell, 1146–1151 (2005)

  5. 5.

    Bruce, J., Thornton, M., Shivakumaraiah, L., Kokate, P., Li, X.: Efficient adder circuits based on a conservative reversible logic gate. The IEEE Computer Society Annual Symposium on VLSI. IEEE, 1–6 (2002)

  6. 6.

    Moghimi, S., Reshadine, M.: A novel 4 × 4 universal reversible gate as a cost efficient full adder/subtractor in terms of reversible and quantum metrices. I.J. Modern Education and Computer Science, 28–34 (2015)

  7. 7.

    Thersesal, T., Sathish, K., Aswinkumor, R.: A new design of optical reversible adder and subtractor using MZI. International Journal of Scientific and Research Oublications 5(4), 1–6 (2015)

    Google Scholar 

  8. 8.

    Fredkin, H., Toffoli, T.: Conservative logic. Int. J. Theor. Phys. 21, 219–253 (1982)

    MathSciNet  Article  MATH  Google Scholar 

  9. 9.

    Thapliyal, H., Ranganathan, N.: Design of efficient reversible binary subtractors based on a new reversible gate. IEEE Computer Society Annual Symposium on VLSI. IEEE, 229–234 (2009)

  10. 10.

    Rangaraju, H., Venugopal, U., Muralidhara, K., Raha, K.: Design of efficient reversible parallel binary adder/subtractor. Computer networks and information technologies, vol. 142, pp 83–37. Springer, Berlin (2011)

    Google Scholar 

  11. 11.

    Kamalakannan, V., Shilpakala, V., Ravi, N.: Design of Adder/Subtractor circuits based on reversible gates. International Journal of Advanced Research in Electrical, Electronics and Instrumentation Engineering, 3796–3804 (2013)

  12. 12.

    Montaser, R., Younes, A., Abdel-Aty, M.: New designs of universal reversible gate library. arXiv:1512.08991v1 [cs.ET], 1–17 (2015)

  13. 13.

    Younes, A.: Tight bounds on the Synthesis of 3-bit reversible circuits: N F F r library. Journal of Circuits Systems and Computers 23(3), 1–22 (2014)

    MathSciNet  Article  Google Scholar 

  14. 14.

    Yang, G., Song, X., Hung, W.N.N., Perkowski, M.A., Seo, C.-J.: Synthesis of reversible circuits with minimal costs. CALCOLO 45, 193–206 (2008)

    MathSciNet  Article  MATH  Google Scholar 

  15. 15.

    Shende, V.V., Prasad, A.K., Markov, I.L., Hayes, J.P.: Synthesis of reversible logic circuits. IEEE T. Comput. Aid. D. 22(6), 710–722 (2003)

    Article  Google Scholar 

  16. 16.

    Maslov, D., Miller, D.M.: Comparison of the cost metrics for reversible and quantum logic synthesis. IET Comput. Digit. Tech. 1(2), 98–104 (2008)

    Article  Google Scholar 

  17. 17.

    Storme, L., De Vos, A., Jacobs, G.: Group theoretical aspects of reversible logic gates. J. Univ. Comput. Sci. 5(5), 307–321 (1999)

    MATH  Google Scholar 

  18. 18.

    Younes, A.: On the universality of n-bit reversible gate libraries. Appl. Math. Inf. Sci. 9(5), 2579–2588 (2015)

    MathSciNet  Google Scholar 

  19. 19.

    Montaser, R., Younes, A., Abdel-Aty, M.: Improving the quantum cost of NCT-based reversible circuit. Quant. Inf. Process., Springer 14(2), 325–351 (2013)

    MATH  Google Scholar 

  20. 20.

    Al Mamuni, S., Menville, D.: Quantum cost optimization for reversible sequential circuit. Int. J. Adv. Comput. Sci. Appl. 4(12), 15–21 (2013)

    Google Scholar 

  21. 21.

    Saha, R., Dalal, S.: A novel reversible combinational circuit design for low power computation. In: Communication and Information Technology Conference (PCITC). IEEE, 1–6 (2015)

  22. 22.

    Lakshmi, A., Sudha, G.: Design of a reversible single precision floating point subtractor. Springer Open Journal, v(3), 1–20 (2014)

  23. 23.

    Thapliyal, H., Ranganathan, N.: A new design of the reversible subtractor circuit. In: 11th IEEE International Conference on Nanotechnology, Portland Marriott, USA, 1430–1435 (2011)

  24. 24.

    Gupta, A., Singla, P., Gupta, J., Maheshwari, N.: An improved structure of reversible adder and subtractor. International Journal of Electronics and Computer Science Engineering 2(2), 712–718 (2013)

    Google Scholar 

  25. 25.

    Hafez, H., Islam, M., Chowdhury, S., Chowshury, A.: Synthesis of full-adder circuit using reversible logic. In: The 17th International Conference on VLSI design, IEEE (2004)

  26. 26.

    Nielsen, M., Chuang, I.: Quantum Computation and Quantum Information, vol. 2000, pp 1–59. Cambridge University Press, Cambridge (2010)

    Book  Google Scholar 

  27. 27.

    De Vos, A.: Reversible computing fundamentals. Quantum computing and applications. Wiley-VCH Verlag GmbH and Co.KGaA, 5–82, 131–166, 183–190 (2010)

  28. 28.

    Islam, M.: A novel quantum cost efficient reversible full adder gate in nanotechnology. arXiv:1008.3533 (2010)

  29. 29.

    Morrison, M., Ranganathan, N.: Design of a reversible ALU based on novel programmable reversible logic gate structures. In: 2011 IEEE computer society annual symposium on VLSICoRR. IEEE, pp. 126–131 (2011)

  30. 30.

    Thapliyal, H.: Mapping of subtractor and adder-subtractor circuits on reversible quantum gates. Transaction on Computer Science XXVII. LNCS, vol. 9570, pp. 10–34. Springer, Heidelberg (2016)

  31. 31.

    Monfared, A., haghparast, M.: Design of novel quantum/reversible ternary adder circuits. International Journal of Electronics Letters 5, 1–14 (2016). Taylor and Francis

    Google Scholar 

  32. 32.

    Kianpour, M., Nadooshan, R.: Novel 8-bit reversible full adder/subtractor using a QCA reversible gate. Journal of Computational Electronics 16, 459–472 (2017). Springer

    Article  Google Scholar 

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Correspondence to Rasha Montaser.

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Montaser, R., Younes, A. & Abdel-Aty, M. New Design of Reversible Full Adder/Subtractor Using R Gate. Int J Theor Phys 58, 167–183 (2019). https://doi.org/10.1007/s10773-018-3921-1

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Keywords

  • Reversible gates
  • Quantum processors
  • Arithmetic unit
  • Reversible adder
  • Reversible subtractor