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Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit

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Abstract

Reversible logic is emerging as a promising alternative for applications in low-power design and quantum computation in recent years due to its ability to reduce power dissipation, which is an important research area in low power VLSI and ULSI designs. Many important contributions have been made in the literatures towards the reversible implementations of arithmetic and logical structures; however, there have not been many efforts directed towards efficient approaches for designing reversible Arithmetic Logic Unit (ALU). In this study, three efficient approaches are presented and their implementations in the design of reversible ALUs are demonstrated. Three new designs of reversible one-digit arithmetic logic unit for quantum arithmetic has been presented in this article. This paper provides explicit construction of reversible ALU effecting basic arithmetic operations with respect to the minimization of cost metrics. The architectures of the designs have been proposed in which each block is realized using elementary quantum logic gates. Then, reversible implementations of the proposed designs are analyzed and evaluated. The results demonstrate that the proposed designs are cost-effective compared with the existing counterparts. All the scales are in the NANO-metric area.

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References

  1. Morrison, M.A.: Design of a Reversible ALU Based on Novel Reversible Logic Structures. PhD diss, Graduate School Theses and Dissertations, University of South Florida (2012)

  2. Morrison, M., Ranganathan, N.: A novel optimization method for reversible logic circuit minimization. In: VLSI (ISVLSI), 2013 IEEE Computer Society Annual Symposium on, pp. 182–187. IEEE (2013)

  3. Grobe, D., Wille, R., Dueck, G.W., Drechsler, R.: Exact synthesis of elementary quantum gate circuits for reversible functions with don’t cares. In: Multiple Valued Logic, 2008. ISMVL 2008. 38th International Symposium on, pp. 214–219. IEEE (2008)

  4. Joonho, L.I.M., Dong-Gyu, K., Soo-Ik, C.H.A.E.: Reversible energy recovery logic circuits and its 8-phase clocked power generator for ultra-low-power applications. IEICE Trans. Electron. 82(4), 646–653 (1999)

    Google Scholar 

  5. Morrison, M., Ranganathan, N.: Design of a reversible ALU based on novel programmable reversible logic gate structures. In: VLSI (ISVLSI), 2011 IEEE Computer Society Annual Symposium on, pp. 126–131. IEEE (2011)

  6. Thomsen, M.K., Glück, R., Axelsen, H.B.: Reversible arithmetic logic unit for quantum arithmetic. J. Phys. A: Math. Theor. 43(38), 382002 (2010)

    Article  MathSciNet  MATH  Google Scholar 

  7. Weste, N.H.E., Harris, D.: CMOS VLSI Design, A Circuits and Systems Perspective. Published by Person Education, 3 ed., Boston: Addison Wesley, 715–738 (2005)

  8. Moore, G.E: Cramming more components onto integrated circuits (1965)

  9. Toffoli, T.: Reversible computing. Springer, Berlin Heidelberg (1980)

    Book  MATH  Google Scholar 

  10. Nielsen, M.A., Chuang, I.L., James, D.F.V.: Quantum computation and quantum information. Phys. Today 54, 60–2 (2001)

    Google Scholar 

  11. Landauer, R.: Irreversibility and heat generation in the computing process. IBM J. Res. Dev. 5(3), 183–191 (1961)

    Article  MathSciNet  MATH  Google Scholar 

  12. Bennett, C.H.: Logical reversibility of computation. IBM J. Res. Dev. 17(6), 525–532 (1973)

    Article  MathSciNet  MATH  Google Scholar 

  13. Dirac, P.A.M.: The principles of quantum mechanics. Oxford, 1958, Chap. 5; for a modern treatment, see A. Peres, Quantum Theory: Concepts and Methods, (Kluwer, 1993), Chap. 8.6 (1930)

  14. Kaye, P., Laflamme, R., Mosca, M.: An introduction to quantum computing. Oxford University Press Book-LinG, published in the United States by Oxford University Press Inc., Oxford, New York, ISBN 0-19-857000-7, pp 799–800 (2007)

  15. Gupta, P., Agrawal, A., Jha, N.K.: An algorithm for synthesis of reversible logic circuits. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 25(11), 2317–2330 (2006)

    Article  Google Scholar 

  16. Wille, R., Drechsler, R.: Towards a design flow for reversible logic. Springer Dordrecht, Heidelberg (2010)

    Book  MATH  Google Scholar 

  17. Hung, W.N.N., Song, X., Yang, G., Yang, J., Perkowski, M.: Quantum logic synthesis by symbolic reachability analysis. In: Proceedings of the 41st annual Design Automation Conference, pp. 838–841. ACM (2004)

  18. Feynman, Richard P.: Quantum mechanical computers. Found. Phys. 16(6), 507–531 (1986)

    Article  ADS  MathSciNet  Google Scholar 

  19. Deutsch, D.: Quantum computational networks. Proc. R. Soc. Lond. A Math. Phys. Sci. 425(1868), 73–90 (1989)

    Article  ADS  MathSciNet  MATH  Google Scholar 

  20. Peres, A.: Reversible logic and quantum computers. Phys. Rev. A 32(6), 3266–3276 (1985)

    Article  ADS  MathSciNet  Google Scholar 

  21. Barenco, A., Bennett, C.H., Cleve, R., DiVincenzo, D.P., Margolus, N., Shor, P., Sleator, T., Smolin, J.A., Weinfurter, H.: Elementary gates for quantum computation. Phys. Rev. A 52(5), 3457 (1995)

    Article  ADS  Google Scholar 

  22. Safari, P., Haghparast, M., Azari, A., Branch, A.: A Design of Fault Tolerant Reversible Arithmetic Logic Unit. Life Science Journal 3, 9 (2012)

    Google Scholar 

  23. Dixit, A., Kapse, V.: Arithmetic & Logic Unit (ALU) Design using Reversible Control Unit. Int. J. Eng. Innov. Technol. (IJEIT), ISSN:2277-3754 1(6), 55–60 (2012)

    Google Scholar 

  24. Syamala, Y., Tilak, A.V.N.: Reversible arithmetic logic unit. In: Electronics Computer Technology (ICECT), 2011 3rd International Conference on, vol. 5, pp. 207-211. IEEE (2011)

  25. Morrison, M., Lewandowski, M., Meana, R., Ranganathan, N.: Design of a novel reversible ALU using an enhanced carry look-ahead adder. In: Nanotechnology (IEEE-NANO), 2011 11th IEEE Conference on, pp. 1436–1440. IEEE (2011)

  26. Guan, Z., Li, W., Ding, W., Hang, Y., Ni, L.: An arithmetic logic unit design based on reversible logic gates. In: Communications, Computers and Signal Processing (PacRim), 2011 IEEE Pacific Rim Conference on, pp. 925–931. IEEE (2011)

  27. Mamatag, S., Das, B., Rahaman, A.: An Optimized Realization of ALU for 12-Operations by using a Control Unit of reversible gates. Int. J. Adv. Res. Comput. Sci. Softw. Eng., ISSN: 2277 128X A. 4(1), 496–502 (2014)

    Google Scholar 

  28. Vedral, V., Barenco, A., Ekert, A.: Quantum networks for elementary arithmetic operations. Phys. Rev. A 54(1), 147–153 (1996)

    Article  ADS  MathSciNet  Google Scholar 

  29. Smolin, J.A., DiVincenzo, D.P.: Five two-bit quantum gates are sufficient to implement the quantum Fredkin gate. Phys. Rev. A 53(4), 2855–6 (1996)

    Article  ADS  MathSciNet  Google Scholar 

  30. Thapliyal, H., Ranganathan, N.: Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. ACM J. Emerg. Technol. Comput. Syst. (JETC) 6(4), 14 (2010)

    Google Scholar 

  31. Qi, X., Chen, F., Guo, L., Luo, Y., Hu, M.: Efficient Approaches for Designing Fault Tolerant Reversible BCD Adders ? J. Comput. Inf. Syst. 9(14), 5869–5877 (2013)

    Google Scholar 

  32. Mohammadi, M., Haghparast, M., Eshghi, M., Navi, K.: Minimization and optimization of reversible BCD-Full adder/subtractor using genetic algorithm and Don’t Care concept. Int. J. Quantum Inf. 05, 969–989 (2009)

    Article  MATH  Google Scholar 

  33. Haghparast, M., Navi, K.: Novel reversible fault tolerant error coding and detection circuits. Int. J. Quantum Inf. 9(02), 723–738 (2011)

    Article  MATH  Google Scholar 

  34. Haghparast, M., Mohammadi, M., Navi, K., Eshghi, M.: Optimized reversible multiplier circuit. J. Circuits Systems Computers 18(02), 311–323 (2009)

    Article  MATH  Google Scholar 

  35. Wille, R., Soeken, M., Drechsler, R.: Reducing the number of lines in reversible circuits. In: Proceedings of the 47th Design Automation Conference (DAC), 47th ACM/IEEE, pp. 647–652. ACM (2010)

  36. Haghparast, M., Jassbi, S.J., Navi, K., Hashemipour, O.: Design of a novel reversible multiplier circuit using HNG gate in nanotechnology. In: World Appl. Sci. J. (2008)

  37. Babazadeh, S., Haghparast, M.: Design of a nanometric fault tolerant reversible multiplier circuit. J. Basic Appl. Sci. Res. 2(2), 1355–1361 (2012)

    Google Scholar 

  38. Haghparast, M., Navi, K.: A novel fault tolerant reversible gate for nanotechnology based systems. Am. J. Appl. Sci. 5(5), 519–523 (2008)

    Article  Google Scholar 

  39. Parhami, B.: Fault-tolerant reversible circuits. In: Signals, Systems and Computers, Pacific Grove, CA 2006, 2006. ACSSC’06. Fortieth Asilomar Conference on, pp. 1726–1729. IEEE (2006)

  40. Islam, M.S., Rahman, M.M., Begum, Z., Hafiz, M.Z.: Low cost quantum realization of reversible multiplier circuit. Inf. Technol. J. 8(2), 208–213 (2009)

    Article  Google Scholar 

  41. Islam, M., Rahman, M.M., Hafiz, M.: Efficient approaches for designing fault tolerant reversible carry look-ahead and carry-skip adders (2010). arXiv:1008.3344

  42. Haghparast, M., Navi, K.: Design of a novel fault tolerant reversible Full Adder for Nanotechnology Based Systems. Am. J. Appl. Sci. 3(1), 114–118 (2008)

    Google Scholar 

  43. Haghparast, M., Navi, K.: A novel reversible BCD adder for nanotechnology based systems. Am. J. Appl. Sci. 5(3), 282–288 (2008)

    Article  Google Scholar 

  44. Shams, M., Haghparast, M., Navi, K.: Novel reversible multiplier circuit in nanotechnology. World Appl. Sci. J. 3(5), 806–810 (2008)

    Google Scholar 

  45. Haghparast, M., Shams, M.: Optimized Nanometric Fault Tolerant Reversible BCD Adder. Res. J. Appl. Sci. Eng. Technol. 4(9), 1067–1072 (2012)

    Google Scholar 

  46. Haghparast, M.: Design and implementation of nanometric fault tolerant reversible BCD adder. Aust. J. Basic Appl. Sci. 5(10), 896–901 (2011)

    Google Scholar 

  47. Maslov, D., Dueck, G.W.: Reversible cascades with minimal garbage. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 23(11), 1497–1509 (2004)

    Article  Google Scholar 

  48. Khan, M.H.A., Perkowski, M.A., Khan, M.R.: Ternary Galois field expansions for reversible logic and Kronecker decision diagrams for ternary GFSOP minimization (Galois field sum of products). In: Multiple-Valued Logic, 2004. Proceedings. 34th International Symposium on, pp. 58–67. IEEE (2004)

  49. Fredkin, E., Toffoli, T.: Conservative logic. Springer, London (2002)

    Book  MATH  Google Scholar 

  50. Zhou, R., Li, Y., Zhang, M., Hu, B.: Novel design for reversible arithmetic logic unit. Int. J. Theor. Phys., 1–15 (2014)

  51. Pradeep, Singla, Satyan: Article: Towards the Solution of Power Dissipation in Electronics Systems through Thermodynamics, Proceedings of ETEIC-2012: April-2012, pp 300–303

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Authors and Affiliations

  1. Department of Computer Engineering, Yadegar -e- Imam Khomeini (RAH) Branch, Islamic Azad University, Tehran, Iran

    Majid Haghparast

  2. Department of Computer Engineering, Arak Branch, Islamic Azad University, Arak, Iran

    Ali Bolhassani

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  1. Majid Haghparast
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  2. Ali Bolhassani
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Correspondence to Majid Haghparast.

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Haghparast, M., Bolhassani, A. Optimization Approaches for Designing Quantum Reversible Arithmetic Logic Unit. Int J Theor Phys 55, 1423–1437 (2016). https://doi.org/10.1007/s10773-015-2782-0

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